SBASAT9 February   2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics - ADC12DL500
    13. 5.13 Typical Characteristics - ADC12DL1500 (1GSPS)
    14. 5.14 Typical Characteristics - ADC12DL1500 (1.5GSPS)
    15. 5.15 Typical Characteristics - ADC12DL2500 (2GSPS)
    16. 5.16 Typical Characteristics - ADC12DL2500 (2.5GSPS)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
        5. 6.3.2.5 Internal Dither
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 LVDS Digital Interface
        1. 6.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 6.3.5.1.1 Dedicated Strobe Pins
          2. 6.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 6.3.5.1.3 LSB Replacement With a Strobe
          4. 6.3.5.1.4 Strobe Over All Data Pairs
      6. 6.3.6 Alarm Monitoring
        1. 6.3.6.1 Clock Upset Detection
      7. 6.3.7 Temperature Monitoring Diode
      8. 6.3.8 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 6.4.2 Internal Dither Modes
      3. 6.4.3 Single-Channel Mode (DES Mode)
      4. 6.4.4 LVDS Output Driver Modes
      5. 6.4.5 LVDS Output Modes
        1. 6.4.5.1 Staggered Output Mode
        2. 6.4.5.2 Aligned Output Mode
        3. 6.4.5.3 Reducing the Number of Strobes
        4. 6.4.5.4 Reducing the Number of Data Clocks
        5. 6.4.5.5 Scrambling
        6. 6.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 6.4.5.6.1 Active Pattern
          2. 6.4.5.6.2 Synchronization Pattern
          3. 6.4.5.6.3 User-Defined Test Pattern
      6. 6.4.6 Power-Down Modes
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 80
        6. 6.5.1.6 Streaming Mode
        7. 6.5.1.7 82
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Reconfigurable Dual-Channel 2.5GSPS or Single-Channel 5GSPS Oscilloscope
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
          3. 7.2.1.1.3 ADC12DLx500
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Maps
    1. 8.1 SPI_REGISTER_MAP Registers
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.3.5.1.1 Dedicated Strobe Pins

Dedicated strobe pins are recommended for applications with robust requirements. Each LVDS bus has a dedicated strobe (DxSTR±), up to four total, which is source synchronous to its associated data clock (DxCLK±). The strobe can run continuously or can be enabled and disabled as needed. When enabled, this mode allows the data bus to still send all 12 bits of the digital samples for highest performance. The tradeoff is that more pins are needed, two per LVDS bus, for up to eight total pins when operating in DMUX-by-2 mode. Table 6-6 describes the strobe output. The SYNC signal is not required to output the dedicated strobe signal.

Table 6-6 Strobe Output for Dedicated Strobe Pins
FRAME SAMPLE NUMBER (UI)1 FRAME (LFRAME = 0x08)
01234567
Dx[11:0]S0[11:0]S1[11:0]S2[11:0]S3[11:0]S4[11:0]S5[11:0]S6[11:0]S7[11:0]
DxSTR00000001