SBASAT9 February 2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500
PRODUCTION DATA
The clocking subsystem of the ADC12DLx500 has two input signals: the device clock (CLK+, CLK–) and SYSREF (SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD adjust), a clock duty cycle corrector, and a SYSREF capture block. Figure 6-2 shows the clocking subsystem.
The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing and LVDS outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment (tAD adjust) allows the sampling instance of the ADC to be shifted in fine steps to synchronize multiple ADC12DLx500 devices or to fine-tune system latency. Duty cycle correction is implemented in the ADC12DLx500 to ease the requirements on the external device clock while maintaining high performance. Table 6-3 summarizes the device clock interface in dual-channel mode and single-channel mode.
MODE OF OPERATION | SAMPLING RATE VS fCLK | SAMPLING INSTANT |
---|---|---|
Dual-channel mode | 1 × fCLK | Rising edge |
Single-channel mode | 2 × fCLK | Rising and falling edge |
SYSREF is a system timing reference used to reset clock dividers and strobe generation within the ADC12DLx500 that is similar to the SYSREF signal used by JESD204B interface devices. SYSREF is used to synchronize multiple ADC12DLx500 devices. SYSREF must be captured by the correct device clock edge to achieve repeatable latency and synchronization. The ADC12DLx500 includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the frame clock frequency. Equation 2 can be used to calculate valid SYSREF frequencies.
where