SBASAT9 February 2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DC ACCURACY | |||||||
Resolution | Resolution with no missing codes | 12 | Bits | ||||
ADC12DL500 | |||||||
DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.17 | LSB | |||
Maximum negative excursion from ideal step size | -0.14 | ||||||
INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 1 | LSB | |||
Maximum negative excursion from ideal transfer function | -1.5 | ||||||
ADC12DL1500 | |||||||
DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.14 | LSB | |||
Maximum negative excursion from ideal step size | -0.14 | ||||||
INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 1 | LSB | |||
Maximum negative excursion from ideal transfer function | -1 | ||||||
ADC12DL2500 | |||||||
DNL | Differential nonlinearity | Maximum positive excursion from ideal step size | 0.17 | LSB | |||
Maximum negative excursion from ideal step size | -0.19 | ||||||
INL | Integral nonlinearity | Maximum positive excursion from ideal transfer function | 2.3 | LSB | |||
Maximum negative excursion from ideal transfer function | -1 | ||||||
ANALOG INPUTS (INA±, INB±) | |||||||
VOFF | Offset Error | CAL_OS = 0 | ±2.0 | mV | |||
CAL_OS = 1 | ±0.3 | mV | |||||
VOFF_ADJ | Input offset voltage adjustment range | Available offset correction range (see CAL_OS bit in the CAL_CFGO register or the OADJ_A_FG0_VINA register) | ±55 | mV | |||
VOFF_ DRIFT | Offset drift | Foreground calibration at nominal temperature only | 14 | µV/°C | |||
Foreground calibration at each temperature | 4 | ||||||
VIN_FSR | Analog differential input full-scale range | Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) | 800 | mVPP | |||
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) | 1040 | ||||||
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) | 480 | ||||||
VIN_FSR_DRIFT | Analog differential input full-scale range drift | Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift | 0.037 | %/°C | |||
Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift | 0.006 | ||||||
VIN_FSR_MATCH | Analog differential input full-scale range matching | Matching between INA± and INB±, default setting, dual channel mode | 0.53 | % | |||
RIN | Single-ended input resistance to AGND | Each input terminal is terminated to AGND, measured at TA = 25°C | 50 | Ω | |||
RIN_ TEMPCO | Input termination linear temperature coefficient | 11.6 | mΩ/°C | ||||
CIN | Single-ended input capacitance | Single-channel mode measured at DC | 0.45 | pF | |||
Dual-channel mode measured at DC | 0.45 | ||||||
TEMPERATURE DIODE CHARACTERISTICS (TDIODE±) | |||||||
ΔVBE | Temperature diode voltage slope | Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Perform offset measurements with the device unpowered or with the PD pin asserted to minimize device self-heating. | -1.5 | mV/°C | |||
BANDGAP VOLTAGE OUTPUT (BG) | |||||||
VBG | Reference output voltage | IL ≤ 100 µA | 1.1 | V | |||
VBG_ DRIFT | Reference output temperature drift | IL ≤ 100 µA | -125 | µV/°C | |||
CLOCK INPUTS (CLK±, SYSREF±, TMSTP±) | |||||||
ZT | Internal termination | Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 | 100 | Ω | |||
Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 | 50 | ||||||
VCM | Input common-mode voltage, self-biased | Self-biasing common-mode voltage for CLK± when AC coupled (DEVCLK_LVPECL_EN must be set to 0) | 0.3 | V | |||
Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1). | 0.3 | ||||||
Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0). | VA11 | ||||||
CL_DIFF | Differential input capacitance | Between positive and negative differential input pins | 0.1 | pF | |||
CL_SE | Single-ended input capacitance | Each input to ground | 0.5 | pF | |||
LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±) | |||||||
VDIFF | Differential output peak-to-peak voltage, DC measurement | Default swing (HSM), 100-Ω load | 720 | mVPP-DIFF | |||
Low swing (LSM), 100-Ω load | 350 | ||||||
Low swing high-Z mode (HZM), high-impedance load | 380 | ||||||
VCM | Output common-mode voltage, tracks with VLVDS | VLVDS = 1.9 V | 1.3 | V | |||
VLVDS = 1.1 V | 0.5 | ||||||
IOS_DIFF | Differential short-circuit current | Positive and negative outputs shorted together | 5 | mA | |||
IOS_GND | Short-circuit current to ground | Either positive or negative output tied to ground | 20 | mA | |||
ZDIFF | Differential output impedance | Measured at DC | 300 | Ω | |||
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE | |||||||
IIH | High-level input current | 40 | µA | ||||
IIL | Low-level input current | –40 | µA | ||||
CI | Input capacitance | 2 | pF | ||||
VOH | High-level output voltage | ILOAD = –400 µA | 1.65 | V | |||
VOL | Low-level output voltage | ILOAD = 400 µA | 150 | mV |