SLVSDR3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-52B9BB54-81F8-4ED0-AC36-1E183834BFBD-low.svgFigure 5-1 ACF Package, 256-Ball Flip Chip BGA
(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
A1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
A2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
A3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
A4 INA+ I Channel A analog input positive connection. The differential full-scale input range is determined by the FS_RANGE_A register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to AGND through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
A5 INA– I Channel A analog input negative connection. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
A6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
A7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
A8 ORA1 O Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used.
A9 DA0+ O LVDS output for bit 0 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
A10 DA0– O LVDS output for bit 0 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
A11 DA6+ O LVDS output for bit 6 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
A12 DA6– O LVDS output for bit 6 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
A13 DC0+ O LVDS output for bit 0 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
A14 DC0– O LVDS output for bit 0 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
A15 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
A16 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
B1 CALSTAT O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used.
B2 CALTRIG I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used.
B3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
B4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
B5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
B6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
B7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
B8 ORA0 O Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used.
B9 DA1+ O LVDS output for bit 1 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
B10 DA1– O LVDS output for bit 1 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
B11 DA7+ O LVDS output for bit 7 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
B12 DA7– O LVDS output for bit 7 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
B13 DC1+ O LVDS output for bit 1 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
B14 DC1– O LVDS output for bit 1 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
B15 DC7+ O LVDS output for bit 7 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
B16 DC7– O LVDS output for bit 7 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
C1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
C8 ORB1 O Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used.
C9 DA2+ O LVDS output for bit 2 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
C10 DA2– O LVDS output for bit 2 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
C11 DA8+ O LVDS output for bit 8 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
C12 DA8– O LVDS output for bit 8 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
C13 DC2+ O LVDS output for bit 2 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
C14 DC2– O LVDS output for bit 2 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
C15 DC8+ O LVDS output for bit 8 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
C16 DC8– O LVDS output for bit 8 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
D1 TMSTP+ I Timestamp input positive connection or differential LVDS SYNC positive connection. This input is used as the timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set 1. This differential input is used as the SYNC signal input when SYNC_SEL is set to 1. This input can be used as both a timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling when used as the LVDS SYNC signal. For additional usage information, see the Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC-coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC-coupled and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC-coupled and DC-coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required.
D2 BG O Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. See the Analog Reference Voltage section for more details. This pin can be left disconnected if not used.
D3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
D4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
D5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
D6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
D7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
D8 ORB0 O Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this pin disconnected if not used.
D9 DA3+ O LVDS output for bit 3 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
D10 DA3– O LVDS output for bit 3 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
D11 DA9+ O LVDS output for bit 9 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
D12 DA9– O LVDS output for bit 9 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
D13 DC3+ O LVDS output for bit 3 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
D14 DC3– O LVDS output for bit 3 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
D15 DC9+ O LVDS output for bit 9 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
D16 DC9– O LVDS output for bit 9 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
E1 TMSTP– I Timestamp input negative connection or differential LVDS SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required.
E2 SYNCSE I LVDS interface SYNC signal, single-ended active low input used to control sending strobe signals for synchronization or digital interface test patterns. The Digital Interface Test Patterns section describes using the SYNC signal in more detail. The choice of single-ended or differential SYNC (using the TMSTP+ and TMSTP– pins) is selected by programming SYNC_SEL. Tie this pin to ground if differential SYNC (TMSTP±) is used as the SYNC signal.
E3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
E4 VA11 I 1.1-V analog supply
E5 VA11 I 1.1-V analog supply
E6 VA11 I 1.1-V analog supply
E7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
E8 VD11 I 1.1-V digital supply
E9 DA4+ O LVDS output for bit 4 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
E10 DA4– O LVDS output for bit 4 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
E11 DA10+ O LVDS output for bit 10 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
E12 DA10– O LVDS output for bit 10 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
E13 DC4+ O LVDS output for bit 4 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
E14 DC4– O LVDS output for bit 4 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
E15 DC10+ O LVDS output for bit 10 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
E16 DC10– O LVDS output for bit 10 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
F1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
F2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
F3 VA11 I 1.1-V analog supply
F4 VA11 I 1.1-V analog supply
F5 VA11 I 1.1-V analog supply
F6 VA11 I 1.1-V analog supply
F7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
F8 VD11 I 1.1-V digital supply
F9 DA5+ O LVDS output for bit 5 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
F10 DA5– O LVDS output for bit 5 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
F11 DA11+ O LVDS output for bit 11 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
F12 DA11– O LVDS output for bit 11 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
F13 DC5+ O LVDS output for bit 5 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
F14 DC5– O LVDS output for bit 5 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
F15 DC11+ O LVDS output for bit 11 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
F16 DC11– O LVDS output for bit 11 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
G1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
G2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
G3 VA19 I 1.9-V analog supply
G4 VA19 I 1.9-V analog supply
G5 VA19 I 1.9-V analog supply
G6 VA19 I 1.9-V analog supply
G7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
G8 VD11 I 1.1-V digital supply
G9 DACLK+ O LVDS output for data clock of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
G10 DACLK– O LVDS output for data clock of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
G11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
G12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
G13 DC6+ O LVDS output for bit 6 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
G14 DC6– O LVDS output for bit 6 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
G15 DCCLK+ O LVDS output for data clock of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
G16 DCCLK– O LVDS output for data clock of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
H1 CLK+ I Device (sampling) clock positive input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both rising and falling edges. In-dual channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0.
H2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
H3 VA19 I 1.9-V analog supply
H4 VA19 I 1.9-V analog supply
H5 VA19 I 1.9-V analog supply
H6 VA19 I 1.9-V analog supply
H7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
H8 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
H9 DASTR+ O LVDS output for data strobe of LVDS bus A. Positive connection. This pin can be left disconnected if not used.
H10 DASTR– O LVDS output for data strobe of LVDS bus A. Negative connection. This pin can be left disconnected if not used.
H11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
H12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
H13 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
H14 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
H15 DCSTR+ O LVDS output for data strobe of LVDS bus C. Positive connection. This pin can be left disconnected if not used.
H16 DCSTR– O LVDS output for data strobe of LVDS bus C. Negative connection. This pin can be left disconnected if not used.
J1 CLK– I Device (sampling) clock negative input. TI strongly recommends that the clock signal be AC-coupled to this input for best performance.
J2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
J3 VA19 I 1.9-V analog supply
J4 VA19 I 1.9-V analog supply
J5 VA19 I 1.9-V analog supply
J6 VA19 I 1.9-V analog supply
J7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
J8 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
J9 DBSTR+ O LVDS output for data strobe of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
J10 DBSTR– O LVDS output for data strobe of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
J11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
J12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
J13 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
J14 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
J15 DDSTR+ O LVDS output for data strobe of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
J16 DDSTR– O LVDS output for data strobe of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
K1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
K2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
K3 VA19 I 1.9-V analog supply
K4 VA19 I 1.9-V analog supply
K5 VA19 I 1.9-V analog supply
K6 VA19 I 1.9-V analog supply
K7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
K8 VD11 I 1.1-V digital supply
K9 DBCLK+ O LVDS output for data clock of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
K10 DBCLK– O LVDS output for data clock of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
K11 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
K12 VLVDS I 1.1-V to 1.9-V LVDS digital interface supply
K13 DD6+ O LVDS output for bit 6 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
K14 DD6– O LVDS output for bit 6 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
K15 DDCLK+ O LVDS output for data clock of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
K16 DDCLK– O LVDS output for data clock of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
L1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
L2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
L3 VA11 I 1.1-V analog supply
L4 VA11 I 1.1-V analog supply
L5 VA11 I 1.1-V analog supply
L6 VA11 I 1.1-V analog supply
L7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
L8 VD11 I 1.1-V digital supply
L9 DB5+ O LVDS output for bit 5 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
L10 DB5– O LVDS output for bit 5 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
L11 DB11+ O LVDS output for bit 11 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
L12 DB11– O LVDS output for bit 11 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
L13 DD5+ O LVDS output for bit 5 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
L14 DD5– O LVDS output for bit 5 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
L15 DD11+ O LVDS output for bit 11 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
L16 DD11– O LVDS output for bit 11 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
M1 SYSREF+ I SYSREF input positive connection. The SYSREF input is used to achieve synchronization between multiple ADC12DL3200 devices and deterministic latency across the LVDS data interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSERF_LVPECL_EN is set to 1. This input is not self-biased when SYSERF_LVPECL is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table.
M2 TDIODE+ I Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.
M3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
M4 VA11 I 1.1-V analog supply
M5 VA11 I 1.1-V analog supply
M6 VA11 I 1.1-V analog supply
M7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
M8 VD11 I 1.1-V digital supply
M9 DB4+ O LVDS output for bit 4 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
M10 DB4– O LVDS output for bit 4 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
M11 DB10+ O LVDS output for bit 10 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
M12 DB10– O LVDS output for bit 10 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
M13 DD4+ O LVDS output for bit 4 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
M14 DD4– O LVDS output for bit 4 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
M15 DD10+ O LVDS output for bit 10 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
M16 DD10– O LVDS output for bit 10 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
N1 SYSREF– I SYSREF input negative connection. See SYSREF+ (pin M1) for detailed description.
N2 TDIODE– I Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
N3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
N4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
N5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
N6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
N7 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
N8 SDO O Serial programming interface (SPI) data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
N9 DB3+ O LVDS output for bit 3 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
N10 DB3– O LVDS output for bit 3 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
N11 DB9+ O LVDS output for bit 9 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
N12 DB9– O LVDS output for bit 9 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
N13 DD3+ O LVDS output for bit 3 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
N14 DD3– O LVDS output for bit 3 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
N15 DD9+ O LVDS output for bit 9 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
N16 DD9– O LVDS output for bit 9 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
P1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
P8 SDI I Serial programming interface (SPI) data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.
P9 DB2+ O LVDS output for bit 2 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
P10 DB2– O LVDS output for bit 2 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
P11 DB8+ O LVDS output for bit 8 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
P12 DB8– O LVDS output for bit 8 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
P13 DD2+ O LVDS output for bit 2 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
P14 DD2– O LVDS output for bit 2 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
P15 DD8+ O LVDS output for bit 8 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
P16 DD8– O LVDS output for bit 8 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
R1 PD I This pin disables all analog circuits and LVDS outputs when set high to save power or for temperature diode calibration. Tie this pin to ground during normal operation.
R2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
R3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
R4 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
R5 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
R6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
R7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
R8 SCS I Serial programming interface (SPI) chip-select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has an 82-kΩ pullup resistor to VD11.
R9 DB1+ O LVDS output for bit 1 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
R10 DB1– O LVDS output for bit 1 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
R11 DB7+ O LVDS output for bit 7 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
R12 DB7– O LVDS output for bit 7 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
R13 DD1+ O LVDS output for bit 1 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
R14 DD1– O LVDS output for bit 1 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
R15 DD7+ O LVDS output for bit 7 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
R16 DD7– O LVDS output for bit 7 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
T1 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
T2 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
T3 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
T4 INB+ I Channel B analog input positive connection. The differential full-scale input range is determined by the FS_RANGE_B register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to AGND through a 50-Ω termination resistor. The input common-mode voltage must typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
T5 INB– I Channel B analog input negative connection. See INB+ (pin T4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
T6 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
T7 AGND — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
T8 SCLK I Serial programming interface (SPI) clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.
T9 DB0+ O LVDS output for bit 0 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
T10 DB0– O LVDS output for bit 0 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
T11 DB6+ O LVDS output for bit 6 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.
T12 DB6– O LVDS output for bit 6 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.
T13 DD0+ O LVDS output for bit 0 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.
T14 DD0– O LVDS output for bit 0 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.
T15 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
T16 DGND — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.