SBASAJ4B June   2022  – October 2024 ADC12QJ1600-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Switching Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
        4. 6.3.1.4 ADC Core
          1. 6.3.1.4.1 ADC Theory of Operation
          2. 6.3.1.4.2 ADC Core Calibration
          3. 6.3.1.4.3 Analog Reference Voltage
          4. 6.3.1.4.4 ADC Over-range Detection
          5. 6.3.1.4.5 Code Error Rate (CER)
      2. 6.3.2 Temperature Monitoring Diode
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 6.3.5 JESD204C Interface
        1. 6.3.5.1  Transport Layer
        2. 6.3.5.2  Scrambler
        3. 6.3.5.3  Link Layer
        4. 6.3.5.4  8B or 10B Link Layer
          1. 6.3.5.4.1 Data Encoding (8B or 10B)
          2. 6.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.5.4.3 Code Group Synchronization (CGS)
          4. 6.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.5.4.5 Frame and Multiframe Monitoring
        5. 6.3.5.5  64B or 66B Link Layer
          1. 6.3.5.5.1 64B or 66B Encoding
          2. 6.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.5.5.3 Initial Lane Alignment
          4. 6.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.5.6  Physical Layer
          1. 6.3.5.6.1 SerDes Pre-Emphasis
        7. 6.3.5.7  JESD204C Enable
        8. 6.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.5.9  Operation in Subclass 0 Systems
        10. 6.3.5.10 Alarm Monitoring
          1. 6.3.5.10.1 Clock Upset Detection
          2. 6.3.5.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Typical Characteristics

Typical values at 25°C, AIN = -1 dBFS, FIN = 347 MHz, FS = 1600 MSPS, High power mode, FG calibration, JMODE 0, C-PLL off, C-PLLREF = 50 MHz and VA11Q and VCLK11 noise suppression on when C-PLL on, Quad Channel operation, nominal supply voltages, unless otherwise noted. SNR results exclude DC and HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

ADC12QJ1600-EP DNL vs Code
Figure 5-1 DNL vs Code
ADC12QJ1600-EP Input Fullscale vs Frequency
Relative to 0Hz
Figure 5-3 Input Fullscale vs Frequency
ADC12QJ1600-EP Single Tone FFT at 347 MHz and -1 dBFS
High power mode, C-PLL on
Figure 5-5 Single Tone FFT at 347 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 847 MHz and -1 dBFS
High power mode
Figure 5-7 Single Tone FFT at 847 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 997 MHz and -1 dBFS
High power mode, C-PLL on, Noise suppression off
Figure 5-9 Single Tone FFT at 997 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 3797 MHz and -1 dBFS
High power mode
Figure 5-11 Single Tone FFT at 3797 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 347 MHz and -1 dBFS
C-PLL on, Low power mode, FS = 1000 MSPS
Figure 5-13 Single Tone FFT at 347 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 2097 MHz and -1 dBFS
Low power mode, FS = 1000 MSPS
Figure 5-15 Single Tone FFT at 2097 MHz and -1 dBFS
ADC12QJ1600-EP SFDR vs Input Frequency
Figure 5-17 SFDR vs Input Frequency
ADC12QJ1600-EP SINAD vs Input Frequency
Figure 5-19 SINAD vs Input Frequency
ADC12QJ1600-EP HD2 vs Input Frequency
Figure 5-21 HD2 vs Input Frequency
ADC12QJ1600-EP SFDR vs Sample Rate
Figure 5-23 SFDR vs Sample Rate
ADC12QJ1600-EP SINAD vs Sample Rate
Figure 5-25 SINAD vs Sample Rate
ADC12QJ1600-EP SFDR vs Sample Rate
Low power mode
Figure 5-27 SFDR vs Sample Rate
ADC12QJ1600-EP SFDR vs Sample Rate
Low power mode
Figure 5-29 SFDR vs Sample Rate
ADC12QJ1600-EP ENOB vs Sample Rate
Low power mode
Figure 5-31 ENOB vs Sample Rate
ADC12QJ1600-EP SNR vs AIN
Figure 5-33 SNR vs AIN
ADC12QJ1600-EP SNR vs AIN
FIN = 100MHz, Low power mode
Figure 5-35 SNR vs AIN
ADC12QJ1600-EP SNR vs ACLK
Figure 5-37 SNR vs ACLK
ADC12QJ1600-EP SFDR vs FREF and Suppression
FIN = 397MHz
Figure 5-39 SFDR vs FREF and Suppression
ADC12QJ1600-EP SNR vs FIN and C-PLL modes
Figure 5-41 SNR vs FIN and C-PLL modes
ADC12QJ1600-EP ENOB vs FIN and C-PLL modes
Figure 5-43 ENOB vs FIN and C-PLL modes
ADC12QJ1600-EP SNR vs FIN and C-PLL modes
Low power mode
Figure 5-45 SNR vs FIN and C-PLL modes
ADC12QJ1600-EP ENOB vs FIN and C-PLL modes
Low power mode
Figure 5-47 ENOB vs FIN and C-PLL modes
ADC12QJ1600-EP SNR vs AIN and C-PLL
Figure 5-49 SNR vs AIN and C-PLL
ADC12QJ1600-EP ENOB vs AIN and C-PLL
Figure 5-51 ENOB vs AIN and C-PLL
ADC12QJ1600-EP HD3 vs AIN and C-PLL
Figure 5-53 HD3 vs AIN and C-PLL
ADC12QJ1600-EP SNR vs AIN and C-PLL
Low power mode
Figure 5-55 SNR vs AIN and C-PLL
ADC12QJ1600-EP ENOB vs AIN and C-PLL
Low power mode
Figure 5-57 ENOB vs AIN and C-PLL
ADC12QJ1600-EP HD3 vs AIN and C-PLL
Low power mode
Figure 5-59 HD3 vs AIN and C-PLL
ADC12QJ1600-EP HD2, HD3 and Worst non-HD Spur vs Supply Voltage
All supplies changed together, high power mode
Figure 5-61 HD2, HD3 and Worst non-HD Spur vs Supply Voltage
ADC12QJ1600-EP HD2, HD3 and Worst non-HD Spur vs Supply Voltage
All supplies changed together, low power mode, FS = 1000MSPS
Figure 5-63 HD2, HD3 and Worst non-HD Spur vs Supply Voltage
ADC12QJ1600-EP SFDR vs Temperature
Figure 5-65 SFDR vs Temperature
ADC12QJ1600-EP HD3 vs Temperature
Figure 5-67 HD3 vs Temperature
ADC12QJ1600-EP Two Tone FFT at 498MHz
10MHz tone spacing
Figure 5-69 Two Tone FFT at 498MHz
ADC12QJ1600-EP Two Tone FFT at 3498MHz
10MHz tone spacing
Figure 5-71 Two Tone FFT at 3498MHz
ADC12QJ1600-EP Two Tone FFT at 1798 MHz
10 MHz tone spacing, -7 dBFS per tone, Low power mode, 1000MSPS
Figure 5-73 Two Tone FFT at 1798 MHz
ADC12QJ1600-EP IMD3 vs FIN
10MHz tone spacing
Figure 5-75 IMD3 vs FIN
ADC12QJ1600-EP Crosstalk to Channel A vs FIN
Figure 5-77 Crosstalk to Channel A vs FIN
ADC12QJ1600-EP Quad Channel, Power Dissipation vs FS and JMODES 0 - 3
Low power background calibration mode
Figure 5-79 Quad Channel, Power Dissipation vs FS and JMODES 0 - 3
ADC12QJ1600-EP Quad Channel, Power Dissipation vs FS and JMODE 8 - 12
Low power background calibration mode
Figure 5-81 Quad Channel, Power Dissipation vs FS and JMODE 8 - 12
ADC12QJ1600-EP Quad Channel, IVA19 vs FS
Low power background calibration mode, independent of JMODE
Figure 5-83 Quad Channel, IVA19 vs FS
ADC12QJ1600-EP Quad Channel, IVD11 vs FS and JMODE 0 - 3
Low power background calibration mode, independent of power mode
Figure 5-85 Quad Channel, IVD11 vs FS and JMODE 0 - 3
ADC12QJ1600-EP Quad Channel, IVD11 vs FS and JMODE 8 - 12
Low power background calibration mode, independent of power mode
Figure 5-87 Quad Channel, IVD11 vs FS and JMODE 8 - 12
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 0 - 3
Low power background calibration mode
Figure 5-89 Dual Channel, Power Dissipation vs FS and JMODE 0 - 3
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 8 - 12
Low power background calibration mode
Figure 5-91 Dual Channel, Power Dissipation vs FS and JMODE 8 - 12
ADC12QJ1600-EP Dual Channel, IVA19 vs FS
Low power background calibration mode, independent of JMODE
Figure 5-93 Dual Channel, IVA19 vs FS
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 0 - 3
Low power background calibration mode, independent of power mode
Figure 5-95 Dual Channel, Power Dissipation vs FS and JMODE 0 - 3
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 8 - 12
Low power background calibration mode, independent of power mode
Figure 5-97 Dual Channel, Power Dissipation vs FS and JMODE 8 - 12
ADC12QJ1600-EP Single Channel, Power Dissipation vs FS and JMODE 0 - 3
Low power background calibration mode
Figure 5-99 Single Channel, Power Dissipation vs FS and JMODE 0 - 3
ADC12QJ1600-EP Single Channel, Power Dissipation vs FS and JMODE 8 - 12
Low power background calibration mode
Figure 5-101 Single Channel, Power Dissipation vs FS and JMODE 8 - 12
ADC12QJ1600-EP Single Channel, IVA19 vs FS
Low power background calibration mode, independent of JMODE
Figure 5-103 Single Channel, IVA19 vs FS
ADC12QJ1600-EP Single Channel, IVD11 vs FS and JMODE 0 - 3
Low power background calibration mode
Figure 5-105 Single Channel, IVD11 vs FS and JMODE 0 - 3
ADC12QJ1600-EP Single Channel, IVD11 vs FS and JMODE 8 - 12
Low power background calibration mode
Figure 5-107 Single Channel, IVD11 vs FS and JMODE 8 - 12
ADC12QJ1600-EP Quad Channel, Power Dissipation Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-109 Quad Channel, Power Dissipation Change with Calibration Mode
ADC12QJ1600-EP Single Channel, Power Dissipation Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-111 Single Channel, Power Dissipation Change with Calibration Mode
ADC12QJ1600-EP Dual Channel, IVA19 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-113 Dual Channel, IVA19 Change with Calibration Mode
ADC12QJ1600-EP Quad Channel, IVA11 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-115 Quad Channel, IVA11 Change with Calibration Mode
ADC12QJ1600-EP Single Channel, IVA11 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-117 Single Channel, IVA11 Change with Calibration Mode
ADC12QJ1600-EP Dual Channel, IVD11 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-119 Dual Channel, IVD11 Change with Calibration Mode
ADC12QJ1600-EP Quad Channel, Power Dissipation vs Temperature
Figure 5-121 Quad Channel, Power Dissipation vs Temperature
ADC12QJ1600-EP Single Channel, Power Dissipation vs Temperature
Figure 5-123 Single Channel, Power Dissipation vs Temperature
ADC12QJ1600-EP Background Calibration Core Transition (offset voltage)
BG Calibration, input voltage offset ~ 90% of fullscale, ADC_SRC_DLY=31, MUX_DLY=30
Figure 5-125 Background Calibration Core Transition (offset voltage)
ADC12QJ1600-EP Background Calibration Core Transition (AC Signal Zoomed)
BG Calibration, ADC_SRC_DLY=31, MUX_DLY=30, unzoomed region shown in previous plot
Figure 5-127 Background Calibration Core Transition (AC Signal Zoomed)
ADC12QJ1600-EP INL vs Code
Figure 5-2 INL vs Code
ADC12QJ1600-EP Single Tone FFT at 347 MHz and -1 dBFS
High power mode
Figure 5-4 Single Tone FFT at 347 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 347 MHz and -1 dBFS
High power mode, C-PLL on, Noise suppression off
Figure 5-6 Single Tone FFT at 347 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 997 MHz and -1 dBFS
High power mode, C-PLL on
Figure 5-8 Single Tone FFT at 997 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 1797 MHz and -1 dBFS
High power mode
Figure 5-10 Single Tone FFT at 1797 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 347 MHz and -1 dBFS
Low power mode, FS = 1000 MSPS
Figure 5-12 Single Tone FFT at 347 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 897 MHz and -1 dBFS
Low power mode, FS = 1000 MSPS
Figure 5-14 Single Tone FFT at 897 MHz and -1 dBFS
ADC12QJ1600-EP Single Tone FFT at 3797 MHz and -1 dBFS
Low power mode, FS = 1000 MSPS
Figure 5-16 Single Tone FFT at 3797 MHz and -1 dBFS
ADC12QJ1600-EP SNR vs Input Frequency
Figure 5-18 SNR vs Input Frequency
ADC12QJ1600-EP ENOB vs Input Frequency
Figure 5-20 ENOB vs Input Frequency
ADC12QJ1600-EP HD3 vs Input Frequency
Figure 5-22 HD3 vs Input Frequency
ADC12QJ1600-EP SNR vs Sample Rate
Figure 5-24 SNR vs Sample Rate
ADC12QJ1600-EP ENOB vs Sample Rate
Figure 5-26 ENOB vs Sample Rate
ADC12QJ1600-EP SNR vs Sample Rate
Low power mode
Figure 5-28 SNR vs Sample Rate
ADC12QJ1600-EP SINAD vs Sample Rate
Low power mode
Figure 5-30 SINAD vs Sample Rate
ADC12QJ1600-EP SFDR vs AIN
Figure 5-32 SFDR vs AIN
ADC12QJ1600-EP SFDR vs AIN
FIN = 100MHz, Low power mode
Figure 5-34 SFDR vs AIN
ADC12QJ1600-EP SFDR vs ACLK
Figure 5-36 SFDR vs ACLK
ADC12QJ1600-EP SNR vs FREF and Suppression
FIN = 397MHz
Figure 5-38 SNR vs FREF and Suppression
ADC12QJ1600-EP SFDR vs FIN and C-PLL modes
Figure 5-40 SFDR vs FIN and C-PLL modes
ADC12QJ1600-EP SINAD vs FIN and C-PLL modes
Figure 5-42 SINAD vs FIN and C-PLL modes
ADC12QJ1600-EP SFDR vs FIN and C-PLL modes
Low power mode
Figure 5-44 SFDR vs FIN and C-PLL modes
ADC12QJ1600-EP SINAD vs FIN and C-PLL modes
Low power mode
Figure 5-46 SINAD vs FIN and C-PLL modes
ADC12QJ1600-EP SFDR vs AIN and C-PLL
Figure 5-48 SFDR vs AIN and C-PLL
ADC12QJ1600-EP SINAD vs AIN and C-PLL
Figure 5-50 SINAD vs AIN and C-PLL
ADC12QJ1600-EP HD2 vs AIN and C-PLL
Figure 5-52 HD2 vs AIN and C-PLL
ADC12QJ1600-EP SFDR vs AIN and C-PLL
Low power mode
Figure 5-54 SFDR vs AIN and C-PLL
ADC12QJ1600-EP SINAD vs AIN and C-PLL
Low power mode
Figure 5-56 SINAD vs AIN and C-PLL
ADC12QJ1600-EP HD2 vs AIN and C-PLL
Low power mode
Figure 5-58 HD2 vs AIN and C-PLL
ADC12QJ1600-EP SNR, SFDR and SINAD vs Supply Voltage
All supplies changed together, high power mode
Figure 5-60 SNR, SFDR and SINAD vs Supply Voltage
ADC12QJ1600-EP SNR, SFDR and SINAD vs Supply Voltages
All supplies changed together, low power mode, FS = 1000MSPS
Figure 5-62 SNR, SFDR and SINAD vs Supply Voltages
ADC12QJ1600-EP SNR vs Temperature
Figure 5-64 SNR vs Temperature
ADC12QJ1600-EP HD2 vs Temperature
Figure 5-66 HD2 vs Temperature
ADC12QJ1600-EP Worst Spur vs Temperature
Worst spur is non-HD2 though -HD10 SDFR
Figure 5-68 Worst Spur vs Temperature
ADC12QJ1600-EP Two Tone FFT at 1798MHz
10MHz tone spacing
Figure 5-70 Two Tone FFT at 1798MHz
ADC12QJ1600-EP Two Tone FFT at 348 MHz
10 MHz tone spacing, -7 dBFS per tone, Low power mode, 1000MSPS
Figure 5-72 Two Tone FFT at 348 MHz
ADC12QJ1600-EP Two Tone FFT at 3498 MHz
10 MHz tone spacing, -7 dBFS per tone, Low power mode, 1000MSPS
Figure 5-74 Two Tone FFT at 3498 MHz
ADC12QJ1600-EP IMD3 vs FIN
10MHz tone spacing, Low power mode, 1000MSPS
Figure 5-76 IMD3 vs FIN
ADC12QJ1600-EP Crosstalk to Channel B vs FIN
Figure 5-78 Crosstalk to Channel B vs FIN
ADC12QJ1600-EP Quad Channel, Power Dissipation vs FS and JMODE 4 - 7
Low power background calibration mode
Figure 5-80 Quad Channel, Power Dissipation vs FS and JMODE 4 - 7
ADC12QJ1600-EP Quad Channel, Power Dissipation vs FS and JMODE 13 - 15
Low power background calibration mode
Figure 5-82 Quad Channel, Power Dissipation vs FS and JMODE 13 - 15
ADC12QJ1600-EP Quad Channel, IVA11 vs FS
Low power background calibration mode, independent of JMODE
Figure 5-84 Quad Channel, IVA11 vs FS
ADC12QJ1600-EP Quad Channel, IVD11 vs FS and JMODE 4 - 7
Low power background calibration mode, independent of power mode
Figure 5-86 Quad Channel, IVD11 vs FS and JMODE 4 - 7
ADC12QJ1600-EP Quad Channel, IVD11 vs FS and JMODE 13 - 15
Low power background calibration mode, independent of power mode
Figure 5-88 Quad Channel, IVD11 vs FS and JMODE 13 - 15
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 4 - 7
Low power background calibration mode
Figure 5-90 Dual Channel, Power Dissipation vs FS and JMODE 4 - 7
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 13 - 15
Low power background calibration mode
Figure 5-92 Dual Channel, Power Dissipation vs FS and JMODE 13 - 15
ADC12QJ1600-EP Dual Channel, IVA11 vs FS
Low power background calibration mode, independent of JMODE
Figure 5-94 Dual Channel, IVA11 vs FS
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 4 - 7
Low power background calibration mode, independent of power mode
Figure 5-96 Dual Channel, Power Dissipation vs FS and JMODE 4 - 7
ADC12QJ1600-EP Dual Channel, Power Dissipation vs FS and JMODE 13 - 15
Low power background calibration mode, independent of power mode
Figure 5-98 Dual Channel, Power Dissipation vs FS and JMODE 13 - 15
ADC12QJ1600-EP Single Channel, Power Dissipation vs FS and JMODE 4 - 7
Low power background calibration mode
Figure 5-100 Single Channel, Power Dissipation vs FS and JMODE 4 - 7
ADC12QJ1600-EP Single Channel, Power Dissipation vs FS and JMODE 13 - 15
Low power background calibration mode
Figure 5-102 Single Channel, Power Dissipation vs FS and JMODE 13 - 15
ADC12QJ1600-EP Single Channel, IVA11 vs FS
Low power background calibration mode, independent of JMODE
Figure 5-104 Single Channel, IVA11 vs FS
ADC12QJ1600-EP Single Channel, IVD11 vs FS and JMODE 4 - 7
Low power background calibration mode
Figure 5-106 Single Channel, IVD11 vs FS and JMODE 4 - 7
ADC12QJ1600-EP Single Channel, IVD11 vs FS and JMODE 13 - 15
Low power background calibration mode
Figure 5-108 Single Channel, IVD11 vs FS and JMODE 13 - 15
ADC12QJ1600-EP Dual Channel, Power Dissipation Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-110 Dual Channel, Power Dissipation Change with Calibration Mode
ADC12QJ1600-EP Quad Channel, IVA19 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-112 Quad Channel, IVA19 Change with Calibration Mode
ADC12QJ1600-EP Single Channel, IVA19 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-114 Single Channel, IVA19 Change with Calibration Mode
ADC12QJ1600-EP Dual Channel, IVA11 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-116 Dual Channel, IVA11 Change with Calibration Mode
ADC12QJ1600-EP Quad Channel, IVD11 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-118 Quad Channel, IVD11 Change with Calibration Mode
ADC12QJ1600-EP Single Channel, IVD11 Change with Calibration Mode
Difference to lower power background calibration, JMODE independent
Figure 5-120 Single Channel, IVD11 Change with Calibration Mode
ADC12QJ1600-EP Dual Channel, Power Dissipation vs Temperature
Figure 5-122 Dual Channel, Power Dissipation vs Temperature
ADC12QJ1600-EP Background Calibration Core Transition (midscale voltage)
BG Calibration, midscale input voltage, ADC_SRC_DLY=31, MUX_DLY=30
Figure 5-124 Background Calibration Core Transition (midscale voltage)
ADC12QJ1600-EP Background Calibration Core Transition (AC Signal)
BG Calibration, ADC_SRC_DLY=31, MUX_DLY=30, zoomed region shown in next plot
Figure 5-126 Background Calibration Core Transition (AC Signal)