SBASAI8A june   2022  – july 2023 ADC12QJ1600-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Revision History
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Switching Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Protection
        2. 8.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.1.3 Analog Input Offset Adjust
        4. 8.3.1.4 ADC Core
          1. 8.3.1.4.1 ADC Theory of Operation
          2. 8.3.1.4.2 ADC Core Calibration
          3. 8.3.1.4.3 Analog Reference Voltage
          4. 8.3.1.4.4 ADC Over-range Detection
          5. 8.3.1.4.5 Code Error Rate (CER)
      2. 8.3.2 Temperature Monitoring Diode
      3. 8.3.3 Timestamp
      4. 8.3.4 Clocking
        1. 8.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 8.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 8.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 8.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 8.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 8.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 8.3.5 JESD204C Interface
        1. 8.3.5.1  Transport Layer
        2. 8.3.5.2  Scrambler
        3. 8.3.5.3  Link Layer
        4. 8.3.5.4  8B or 10B Link Layer
          1. 8.3.5.4.1 Data Encoding (8B or 10B)
          2. 8.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.5.4.3 Code Group Synchronization (CGS)
          4. 8.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.5.4.5 Frame and Multiframe Monitoring
        5. 8.3.5.5  64B or 66B Link Layer
          1. 8.3.5.5.1 64B or 66B Encoding
          2. 8.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 8.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 8.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 8.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 8.3.5.5.3 Initial Lane Alignment
          4. 8.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.5.6  Physical Layer
          1. 8.3.5.6.1 SerDes Pre-Emphasis
        7. 8.3.5.7  JESD204C Enable
        8. 8.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 8.3.5.9  Operation in Subclass 0 Systems
        10. 8.3.5.10 Alarm Monitoring
          1. 8.3.5.10.1 Clock Upset Detection
          2. 8.3.5.10.2 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. 8.4.2.1 JESD204C Transport Layer Data Formats
        2. 8.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 8.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1. 8.4.4.1 Serializer Test-Mode Details
        2. 8.4.4.2 PRBS Test Modes
        3. 8.4.4.3 Clock Pattern Mode
        4. 8.4.4.4 Ramp Test Mode
        5. 8.4.4.5 Short and Long Transport Test Mode
          1. 8.4.4.5.1 Short Transport Test Pattern
        6. 8.4.4.6 D21.5 Test Mode
        7. 8.4.4.7 K28.5 Test Mode
        8. 8.4.4.8 Repeated ILA Test Mode
        9. 8.4.4.9 Modified RPAT Test Mode
      5. 8.4.5 Calibration Modes and Trimming
        1. 8.4.5.1 Foreground Calibration Mode
        2. 8.4.5.2 Background Calibration Mode
        3. 8.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 8.4.6 Offset Calibration
      7. 8.4.7 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
      7. 8.5.7 SPI_Register_Map Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Front-End Requirements
          2. 9.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 9.2.1.3 Application Curves
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Sequencing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 JESD204C Modes

The device can be programmed for a number JESD204C output formats. Table 8-13 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.

Table 8-13 ADC12QJ1600-SP Operating Mode Configuration Parameters
PARAMETER DESCRIPTION USER CONFIGURED OR DERIVED VALUE
JMODE JESD204C operating mode, automatically derives the rest of the JESD204C parameters User configured Set by JMODE
R Number of bits transmitted per lane per ADC core sampling clock cycle. The JESD204C line rate is the sampling clock frequency (fS) times R. This parameter sets the SerDes PLL multiplication factor. Derived See Table 8-15
K Number of frames per multiframe (8B/10B mode) User configured Set by KM1, see the allowed values in Table 8-15. This parameter is ignored in 64B/66B modes.
E Number of multiblocks per extended multiblock (64B/66B mode) Derived Always set to '1' in ADC12QJ1600-SP. This parameter is ignored in 8B/10B modes.

There are a number of parameters required to define the JESD204C transport layer format, all of which are sent across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the ILAS, however the transport layer uses the same parameters. In the device, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. Table 8-14 describes these parameters.

Table 8-14 JESD204C Initial Lane Alignment Sequence Parameters
PARAMETER DESCRIPTION USER CONFIGURED OR DERIVED VALUE
ADJCNT LMFC adjustment amount (not applicable) Derived Always 0
ADJDIR LMFC adjustment direction (not applicable) Derived Always 0
BID Bank ID Derived Always 0
CF Number of control words per frame Derived Always 0
CS Control bits per sample Derived Always set to 0 in ILAS, see Table 8-15 for actual usage
DID Device identifier, used to identify the link User configured Set by DID, see Table 8-16
F Number of octets (bytes) per frame (per lane) Derived See Table 8-15
HD High-density format (samples split between lanes) Derived Always 0
JESDV JESD204 standard revision Derived Always 1
K Number of frames per multiframe User configured Set by the KM1 register
L Number of serial output lanes per link Derived See Table 8-15
LID Lane identifier for each lane Derived See Table 8-16
M Number of converters used to determine lane bit packing; may not match number of ADC channels in the device Derived See Table 8-15
N Sample resolution (before adding control and tail bits) Derived See Table 8-15
N' Bits per sample after adding control and tail bits Derived See Table 8-15
S Number of samples per converter (M) per frame Derived See Table 8-15
SCR Scrambler enabled User configured Set by SCR
SUBCLASSV Device subclass version Derived Always 1
RES1 Reserved field 1 Derived Always 0
RES2 Reserved field 2 Derived Always 0
CHKSUM Checksum for ILAS checking (sum of all above parameters modulo 256) Derived Computed based on parameters in this table

Configuring the device is made easy by using a single configuration parameter called JMODE. Using Table 8-15 the correct JMODE value can be found for the desired operating mode. The modes listed are the only available operating modes. This tables also gives a range and allowable step size for the K parameter (set by KM1), which sets the multiframe length in number of frames.

Table 8-15 Operating Modes for Quad Channel Device
OPERATING MODE USER-SPECIFIED PARAMETER DERIVED PARAMETERS INPUT CLOCK RANGE (MHz)
JMODE K
[Min:Step:Max]		 Encoding N CS N’ CF L M F S HD E R
(Fbit / Fclk)
12-Bit, 8B/10B, 8 Lanes 0 4:4:256 8B/10B 12 0 12 0 8 8(1) 8 5 0 — 8 500-1600
12-Bit, 8B/10B, 6 Lanes 1 16:16:256 8B/10B 12 0 12 0 6 4 2 2 1 — 10 500-1600
8-Bit, 8B/10B, 4 Lanes 2 32:32:256 8B/10B 8 0 8 0 4 4 1 1 0 — 10 500-1600
10-Bit, 8B/10B, 4 Lanes 3 32:32:256 8B/10B 10 0 10 0 4 4 5 4 0 — 12.5 500-1372.8
12-Bit, 64B/66B, 3 Lanes 4 128(2) 64B/66B 12 0 12 0 3 4 2 1 1 1 16.5 500-1040
8-Bit, 64B/66B, 2 Lanes 5 128(2) 64B/66B 8 0 8 0 2 4 2 1 0 1 16.5 500-1040
12-Bit, 64B/66B, 6 Lanes 6 128(2) 64B/66B 12 0 12 0 6 4 2 2 1 1 8.25 500-1600
8-Bit, 64B/66B, 4 Lanes 7 256(2) 64B/66B 8 0 8 0 4 4 1 1 0 1 8.25 500-1600
12-Bit, 64B/66B, 4 Lanes 8 256(2) 64B/66B 12 0 12 0 4 4 3 2 0 3 12.375 500-1386.7
8-Bit, 8B/10B, 8 Lanes 9 32:32:256 8B/10B 8 0 8 0 8 4 1 2 0 — 5 500-1600
10-Bit, 8B/10B, 8 Lanes 10 32:32:256 8B/10B 10 0 10 0 8 8(1) 5 4 0 — 6.25 500-1600
2 Ch, 12-Bit, 8B/10B, 8 Lanes 11 4:4:256 8B/10B 12 0 12 0 8 8(1) 8 5 0 — 4 500-1600
2 Ch, 8-Bit, 8B/10B, 8 Lanes 12 32:32:256 8B/10B 8 0 8 0 8 2 1 4 0 — 2.5 500-1600
2 Ch, 10-Bit, 8B/10B, 8 Lanes 13 32:32:256 8B/10B 10 0 10 0 8 8(1) 5 4 0 — 3.125 500-1600
12-Bit, 64B/66B, 8 Lanes 14 256(2) 64B/66B 12 0 12 0 8 8(1) 3 2 0 3 6.1875 500-1600
2-ch, 12-Bit, 64B/66B, 8 Lanes 15 256(2) 64B/66B 12 0 12 0 8 8(1) 3 2 2 3 3.09375 500-1600
(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see mode diagrams for more details.
(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x E/F. K is not an actual parameter of the 64B/66B link layer.

The device has a total of 8 high-speed output drivers. The lanes and their derived configuration parameters are described in Table 8-16. For a specified JMODE, the lowest indexed lanes are used and the higher indexed lanes are automatically powered down. Always route the lowest indexed lanes to the logic device.

Table 8-16 ADC12QJ1600-SP Lane Assignment and Parameters
DEVICE PIN DESIGNATION DID (User Configured) LID (Derived)
D0± Set by DID 0
D1± Set by DID 1
D2± Set by DID 2
D3± Set by DID 3
D4± Set by DID 4
D5± Set by DID 5
D6± Set by DID 6
D7± Set by DID 7