SBASAG0A October   2021  – October 2024 ADC12DJ800 , ADC12QJ800 , ADC12SJ800

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation

An internal PLL with integrated VCO, called the converter PLL (C-PLL), is available for the high-speed sampling clock generation from a low-frequency reference signal to simplify system clocking architectures and to avoid routing of high speed clocks around the circuit board. The C-PLL architecture is shown in Figure 6-6. The PLL is enabled by setting the PLL_EN pin high.

ADC12QJ800 ADC12DJ800 ADC12SJ800 Converter PLL (C-PLL) ArchitectureFigure 6-6 Converter PLL (C-PLL) Architecture

The PLL takes a low-frequency reference clock from the CLK± pins if the PLLREF_SE pin is set low or the SE_CLK pin if the PLLREF_SE pin is set high. The reference clock is applied directly to the phase-frequency detector (PFD). The PFD compares the reference clock phase to the phase of the clock divided-down from the VCO. Therefore, the VCO frequency (fVCO) divided by all of the dividers in the path (V, P, N) must be equal to the reference clock frequency (fREF). The sampling frequency (fS) is then the reference frequency times the N divider or the VCO frequency divided by the V and P dividers. The equations governing the PLL operation are given by Equation 2 and Equation 3.

Equation 2. fS = fVCO ÷ (V × P)

where

  • fS is the ADC core sampling rate
  • fVCO is the VCO frequency
  • V is the VCO divider
  • P is the VCO prescalar
Equation 3. fREF × N = fS

where

  • fREF is the PLL reference frequency
  • N is the PLL feedback divider

Equation 4 can be used to calculate the product of the V and P dividers (V × P). Simply choose V and P such that their product equals the calculated product. Equation 5 can be used to calculate the N divider based on the desired sampling rate and reference frequency.

Equation 4. V × P = fVCO ÷ fS
Equation 5. N = fS ÷ fREF

The VCO in the device has a limited tuning range which limits the ADC sampling rates that can be generated by the PLL. The available VCO divisors (product of P and V) and resulting sampling rates are provided in Table 6-4. Only the sampling rates in Table 6-4 are available in the device when the PLL is enabled. If the desired sampling rate is not supported by the PLL then the PLL must be disabled and the desired sampling clock provided to the CLK± pins.

Table 6-4 Available VCO Divisors and Achievable ADC Sampling Rates
VCO Divisor (P × V)Minimum ADC Core Sampling RateMaximum ADC Core Sampling Rate
10720 MSPS800 MSPS
12600 MSPS683 MSPS
16500 MSPS513 MSPS

The C-PLL should be held in reset before changing any of the C-PLL settings by setting register CPLL_RESET to 1 (address = 0x5C CPLL_RESET). The C-PLL dividers can be programmed using registers PLL_P_DIV (address = 0x3D CPLL_FBDIV1), PLL_V_DIV (address = 0x03D CPLL_FBDIV1) and PLL_N_DIV (address = 0x3E CPLL_FBDIV2). After programming the dividers the VCO calibration should be run by first setting register VCO_CAL_EN to 1 (address = 0x5D VCO_CAL_CNTL). The VCO calibration is run when register CPLL_RESET (address = 0x5C CPLL_RESET) is set to 0 to take the C-PLL out of reset. Calibration is finished and the C-PLL is locked when register VCO_CAL_DONE (address = 0x5E VCO_CAL_STATUS) returns 1 and register CPLL_LOCKED (address = 0x208 JESD_STATUS) is 1.

The C-PLL includes noise suppression options for the VA11Q and VCLK11 that reduce the sampling jitter and reference clock input spur at the expense of approximately 20mA of current each. The control bits are found in the CLK_CTRL2 register (address = 0x2B CLK_CTRL2).