The input to the clocking subsystem of the device includes two clock inputs (CLK± and SE_CLK) and a synchronization signal (SYSREF±). An internal phase-locked loop (PLL) and voltage-controlled oscillator (VCO) can optionally be used to generate the ADC sampling clock from a low frequency reference by setting the PLL_EN pin high. The sampling clock PLL is called the converter PLL (C-PLL). The C-PLL reference can be provided to either the CLK± differential input or the SE_CLK single-ended input. The single-ended C-PLL reference input is selected by setting the PLLREF_SE pin high. For highest performance, the internal C-PLL can be bypassed and the sampling clock provided directly to the CLK± input when PLL_EN and PLLREF_SE are held low. Note that SE_CLK cannot be used if the C-PLL is disabled. The C-PLL reference clock can be sent to either an FPGA or ASIC or to an adjacent device through the PLLREFO± LVDS output when the PLL is enabled. Two additional copies or divided copies of PLLREFO can be output on ORC and ORD when enabled through the CLKCFG[1:0] pins or through SPI. PLLREFO and the ORC and ORD clock outputs are available at device power up when the CMOS control pins (PLL_EN, CLKCFG0 and CLKCFG1) are set appropriately and if PD is held low. Toggling PD high to power down the device also powers down the clock outputs.

In addition, the SerDes block contains a PLL, called S-PLL, that generates the SerDes output clock from the ADC sampling clock. The S-PLL generated clock can be divided and output from the TRIGOUT± LVDS output and sent to an FPGA or ASIC to clock the SerDes receivers. The SYSREF signal is captured by the chosen clock input (CLK± or SE_CLK). A SYSREF Windowing block is used to measure and optimize the setup and hold timing of the SYSREF signal relative to the selected clock input. SYSREF Windowing relaxes the timing requirement of the external signals. Figure 7-5 shows the clocking subsystem.

Figure 7-5 Clocking Subsystem

The clock generated by the C-PLL when the PLL is enabled or the clock provided to CLK± when the PLL is disabled is used as the sampling clock for the ADC core as well as the clocking for the digital processing and serializer S-PLL. Use a low-noise (low jitter) clock input, whether the PLL is enabled or disabled, to maintain high signal-to-noise ratio (SNR) within the ADC.