SBASAE0A October   2021  – November 2024 ADC12DJ1600 , ADC12QJ1600 , ADC12SJ1600

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
        4. 7.3.1.4 ADC Core
          1. 7.3.1.4.1 ADC Theory of Operation
          2. 7.3.1.4.2 ADC Core Calibration
          3. 7.3.1.4.3 Analog Reference Voltage
          4. 7.3.1.4.4 ADC Over-range Detection
          5. 7.3.1.4.5 Code Error Rate (CER)
      2. 7.3.2 Temperature Monitoring Diode
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 7.3.4.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 7.3.4.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 7.3.4.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 7.3.4.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 7.3.4.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 JESD204C Interface
        1. 7.3.5.1  Transport Layer
        2. 7.3.5.2  Scrambler
        3. 7.3.5.3  Link Layer
        4. 7.3.5.4  8B or 10B Link Layer
          1. 7.3.5.4.1 Data Encoding (8B or 10B)
          2. 7.3.5.4.2 Multiiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.5.4.3 Code Group Synchronization (CGS)
          4. 7.3.5.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.5.4.5 Frame and Multiframe Monitoring
        5. 7.3.5.5  64B or 66B Link Layer
          1. 7.3.5.5.1 64B or 66B Encoding
          2. 7.3.5.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 7.3.5.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 7.3.5.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 7.3.5.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 7.3.5.5.3 Initial Lane Alignment
          4. 7.3.5.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.5.6  Physical Layer
          1. 7.3.5.6.1 SerDes Pre-Emphasis
        7. 7.3.5.7  JESD204C Enable
        8. 7.3.5.8  Multi-Device Synchronization and Deterministic Latency
        9. 7.3.5.9  Operation in Subclass 0 Systems
        10. 7.3.5.10 Alarm Monitoring
          1. 7.3.5.10.1 Clock Upset Detection
          2. 7.3.5.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Power Mode and High Performance Mode
      2. 7.4.2 JESD204C Modes
        1. 7.4.2.1 JESD204C Transport Layer Data Formats
        2. 7.4.2.2 64B or 66B Sync Header Stream Configuration
        3. 7.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 7.4.3 Power-Down Modes
      4. 7.4.4 Test Modes
        1. 7.4.4.1 Serializer Test-Mode Details
        2. 7.4.4.2 PRBS Test Modes
        3. 7.4.4.3 Clock Pattern Mode
        4. 7.4.4.4 Ramp Test Mode
        5. 7.4.4.5 Short and Long Transport Test Mode
          1. 7.4.4.5.1 Short Transport Test Pattern
        6. 7.4.4.6 D21.5 Test Mode
        7. 7.4.4.7 K28.5 Test Mode
        8. 7.4.4.8 Repeated ILA Test Mode
        9. 7.4.4.9 Modified RPAT Test Mode
      5. 7.4.5 Calibration Modes and Trimming
        1. 7.4.5.1 Foreground Calibration Mode
        2. 7.4.5.2 Background Calibration Mode
        3. 7.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 7.4.6 Offset Calibration
      7. 7.4.7 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
      2. 7.5.2 SCS
      3. 7.5.3 SCLK
      4. 7.5.4 SDI
      5. 7.5.5 SDO
      6. 7.5.6 Streaming Mode
      7. 7.5.7 SPI_Register_Map Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Analog Front-End Requirements
          2. 8.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.3 Application Curves

An example pulse measurement using the device is shown in Figure 8-2. The setup follows the example LiDAR system requirements with a 5-ns pulse captured at 1 GSPS. The applied pulse has a rise and fall time of approximately 1 ns. A sub-sampling technique is used to interpolate data points to form an equivalent 32 GSPS capture of the pulse for more accurate details and multiple capture averaging is used to suppress noise. A negative DC bias is applied to the ADC to enable use of the full dynamic range of the ADC for unipolar pulses. The pulse is spanning almost the full range of ADC codes. The extracted pulse parameters are given in Table 8-3. The analog front-end is not included in this measurement.

ADC12QJ1600 ADC12DJ1600 ADC12SJ1600 Measured Pulse using Sub-Sampling Technique for Equivalent 32 GSPS MeasurementFigure 8-2 Measured Pulse using Sub-Sampling Technique for Equivalent 32 GSPS Measurement
Table 8-3 Extracted Pulse Parameters for Example LiDAR System
Measured ParameterMeasured ValueUnits
Rise Time (10-90%)1.18ns
Fall Time (90-10%)1.19ns
Pulse Width (50%)4.99ns
Equivalent Bandwidth(1)295.3MHz
Peak Amplitude (Codes)3901LSB
Peak Amplitude (Voltage)750.5mV
DC Offset (Codes)-1994LSB
DC Offset (Voltage)-383.7mV
(1) The equivalent bandwidth is calculated from the extracted rise time measurement. The bandwidth is limited by a 1-ns transition time converter used at the output of the pulse generator.