SNAS378L November   2008  – February 2019 ADC14155QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Block Diagram
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Descriptions and Equivalent Circuits
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  ADC14155 Converter Electrical Characteristics DC Parameters
    6. 6.6  ADC14155 Converter Electrical Characteristics (Continued) DYNAMIC Parameters
    7. 6.7  ADC14155 Converter Electrical Characteristics (Continued) Logic and Power Supply Electrical Characteristics
    8. 6.8  ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics
    9. 6.9  Timing Diagram
    10. 6.10 Transfer Characteristic
    11. 6.11 Typical Performance Characteristics, DNL, INL
    12. 6.12 Typical Performance Characteristics, Dynamic Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Differential Analog Input Pins
        2. 7.3.1.2 Driving The Analog Inputs
        3. 7.3.1.3 Input Common Mode Voltage
      2. 7.3.2 Reference Pins
      3. 7.3.3 Digital Inputs
        1. 7.3.3.1 Clock Inputs
        2. 7.3.3.2 Power-Down (PD)
        3. 7.3.3.3 Clock Mode Select/Data Format (CLK_SEL/DF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Radiation Environments
      1. 8.3.1 Total Ionizing Dose (TID)
      2. 8.3.2 Single Event Effects
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NBA|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

Digital outputs consist of the 1.8 V CMOS signals D0-D13, DRDY and OVR.

The ADC14155 has 16 CMOS compatible data output pins: 14 data output bits corresponding to the converted input value, a data ready (DRDY) signal that should be used to capture the output data and an over-range indicator (OVR) which is set high when the sample amplitude exceeds the 14-bit conversion range. Valid data is present at these outputs while the PD pin is low.

Data should be captured and latched with the rising edge of the DRDY signal. Depending on the setup and hold time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the DRDY signal can be used to latch the data. Generally, rising-edge capture would maximize setup time with minimal hold time; while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the ASIC. Refer to the ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics table.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 5 pF/pin will cause tOD to increase, reducing the setup and hold time of the ADC output data. The result could be an apparent reduction in dynamic performance.

To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can be done by using a programmable logic device (PLD) such as the LC4032V-25TN48C to level translate the ADC output data from 1.8 V to 3.3 V for use by any other circuitry. Only one load should be connected to each output pin. Additionally, inserting series resistors of about 22 Ω at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 24.