SLASE49B December   2015  – April 2017 ADC14X250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Static Converter Performance
    6. 6.6  Electrical Characteristics: Dynamic Converter Performance
    7. 6.7  Electrical Characteristics: Power Supply
    8. 6.8  Electrical Characteristics: Analog Interface
    9. 6.9  Digital Input Characteristics
    10. 6.10 Electrical Characteristics: Serial Data Output Interface
    11. 6.11 Electrical Characteristics: Digital Input
    12. 6.12 Timing Requirements
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 JESD204B Interface Functional Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  Input Clock Divider
      3. 8.3.3  SYSREF Offset Feature and Detection Gate
      4. 8.3.4  DC Offset Correction
      5. 8.3.5  Serial Differential Output Drivers
        1. 8.3.5.1 De-Emphasis Equalization
      6. 8.3.6  ADC Core Calibration
      7. 8.3.7  Data Format
      8. 8.3.8  JESD204B Supported Features
      9. 8.3.9  Transport Layer Configuration
        1. 8.3.9.1 Lane Configuration
        2. 8.3.9.2 Frame Format
        3. 8.3.9.3 ILA Information
      10. 8.3.10 Test Pattern Sequences
      11. 8.3.11 JESD204B Link Initialization
        1. 8.3.11.1 Frame Alignment
        2. 8.3.11.2 Code Group Synchronization
      12. 8.3.12 Sync~ Signal Selection
      13. 8.3.13 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
        1. 8.5.1.1  CONFIG_A, [Address: 0x0000], [Default: 0x3C]
        2. 8.5.1.2  DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]
        3. 8.5.1.3  CHIP_TYPE, [Address: 0x0003], [Default: 0x03]
        4. 8.5.1.4  CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]
        5. 8.5.1.5  CHIP_VERSION, [Address: 0x0006], [Default: 0x00]
        6. 8.5.1.6  VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]
        7. 8.5.1.7  SPI_CFG, [Address: 0x0010], [Default: 0x01]
        8. 8.5.1.8  OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]
        9. 8.5.1.9  OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]
        10. 8.5.1.10 IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]
        11. 8.5.1.11 DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]
        12. 8.5.1.12 SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]
        13. 8.5.1.13 JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]
        14. 8.5.1.14 JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]
        15. 8.5.1.15 JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]
        16. 8.5.1.16 JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Clock Configuration Examples
        4. 9.1.4.4 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Design Procedure
      3. 9.2.3 Application Performance Plot
      4. 9.2.4 Systems Example
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 Specification Definitions
        2. 12.1.1.2 JESD204B Definitions
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Device and Documentation Support

12.1 Device Support

12.1.1 Related Documentation

See the Isolation Glossary (SLLA353)

12.1.1.1 Specification Definitions

    3-dB BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental deviates 3 dB from its low frequency value relative to the differential voltage signal applied at the device input pins.
    APERTURE DELAY is the time delay between the rising edge of the clock until the input signal is acquired or held for conversion.
    APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
    CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the total time of one period. The specification here refers to the ADC clock input signal.
    COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both terminals of the ADC differential input.
    COMMON MODE REJECTION RATIO (CMRR) is the ratio of the magnitude of the single-tone spur in the sampled spectrum (referred to the ADC analog input as a peak voltage quantity) to the peak voltage swing of a sinusoid simultaneously incident on the positive and negative terminals of a differential analog input as a common-mode signal from which the spur generated. CMRR is typically expressed in decibels [dB].
    DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 least significant bit (LSB)
    GAIN VARIATION is the expected standard deviation in the gain of the converter from an applied voltage to output codes between parts or between channels.
    INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a best-fit straight line. The deviation of any given code from this straight line is measured from the center of that code value.
    INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It quantifies the power of the largest intermodulation product adjacent to the input tones, expressed in dBFS.
    LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits. This value is VFS / 2n, where VFSis the full scale input voltage and n is the ADC resolution in bits.
    MISSING CODES are those output codes that do not appear at the ADC outputs. The ADC14X250 device is specified not to have missing codes.
    MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight. Its value is one half of full scale.
    OFFSET ERROR is the difference between the two input voltages (VIN+ – VIN–) required to cause a transition from code 8191LSB and 8192LSB with offset binary data format.
    POWER SUPPLY SENSITIVITY is a measure of the sensitivity of the power supplies to noise. In this specification, a supply is modulated with a 100-mV, 500-kHz sinusoid and the resulting spurs in the spectrum are measured. The sensitivity is expressed relative to the power of a possible full-scale sinusoid [dBFS].
    SAMPLE-TO-SERIAL OUT (S2SO) LATENCY is the number of frame clock cycles between initiation of conversion and the time when the first bit of serial data for that sample is present at the output driver. This latency is not specified to be deterministic.
    SAMPLE-TO-PARALLEL OUT (S2PO) LATENCY is the number of frame clock cycles between initiation of conversion and the time when the parallel sample data is available at the output of the receiver’s elastic buffer. This latency is specified to be deterministic if the JESD204B subclass 1 requirements are satisfied.
    SIGNAL-TO-NOISE RATIO (SNR) is the ratio, expressed in dB, of the power of the input signal to the total power of all other spectral components, not including harmonics and DC. SNR is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].
    SIGNAL-TO-NOISE AND DISTORTION (SINAD) is the ratio, expressed in dB, of the power of the input signal to the total power of all of the other spectral components, including harmonics but excluding DC. SINAD is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].
    NON-HD2/HD3 SPUR is the ratio, expressed in dB, of the power of the peak spurious signal to the power of the input signal, where a spurious signal is any signal present in the output spectrum that is not present at the input excluding the second and third harmonic distortion. This parameter is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].
    SPURIOUS FREE DYNAMIC RANGE (SFDR) is the ratio, expressed in dB, of the input signal power to the peak spurious signal power, where a spurious signal is any signal present in the output spectrum that is not present at the input. SINAD is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].
    SECOND HARMONIC DISTORTION (2ND HARM or HD2) is the ratio, expressed in dB, of the power of the input signal’s 2nd harmonic to the power of the input signal. HD2 is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].
    THIRD HARMONIC DISTORTION (3RD HARM or HD3) is the ratio, expressed in dB, of the power of the input signal’s 3rd harmonic to the power of the input signal. HD3 is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].
    TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total power of the first eight harmonics (HD2 through HD9) to the input signal power. THD is usually expressed relative to the power of a possible full-scale sinusoid [dBFS] or relative to the power of the actual input carrier signal [dBc].

12.1.1.2 JESD204B Definitions

    DEVICE CLOCK is a master clock signal from which a device must generate its local frame and local multi-frame clocks. For the ADC14X250 device, this refers to the signal at the CLKIN input.
    FRAME is a set of consecutive octets in which the position of each octet can be identified by references to a frame alignment signal.
    FRAME CLOCK is a signal used for sequencing frames or monitoring their alignment. For the ADC14X250 device, this clock is internally generated and is not externally accessible.
    LINK (DATA LINK) is an assembly, consisting of parts of two devices and the interconnecting data circuit, that is controlled by a long protocol enabling data to be transferred from a data source to a data sink. The link includes portions of the ADC14X250 device (transmitter), FPGA or ASIC (receiver), and the hardware that connects them.
    LOCAL MULTI-FRAME CLOCK (LMFC) is a signal used for sequencing multi-frames or monitoring their alignment. This clock is derived inside the ADC14X250 device from the device clock and used in the implementation of the JESD204B link within the device.
    MULTI-FRAME is a set of consecutive frames in which the position of each frame can be identified by reference to a multi-frame alignment signal.
    OCTET is a group of eight adjacent binary digits, serving as the input to an 8B/10B encoder or the output of an 8B/10B decoder.
    SCRAMBLING is the randomization of the output data that is used to eliminate long strings of consecutive identical transmitted symbols and avoid the presence of spectral lines in the signal spectrum without changing the signaling rate.
    SERIAL LANE is a differential signal pair for data transmission in one direction.
    SYSREF is a periodic, one-shot, or gapped periodic signal used to align the boundaries of local multi-frame clocks in JESD204B subclass 1 compliant devices. SYSREF must be source synchronous with the device clock.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

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12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.