The ADC16DX370 device is a monolithic dual-channel high performance analog-to-digital converter capable of converting analog input signals into 16-bit digital words with a sampling rate of 370 MSPS. This converter uses a differential pipelined architecture with integrated input buffer to provide excellent dynamic performance while maintaining low power consumption.
The integrated input buffer eliminates charge kickback noise coming from the internal switched capacitor sampling circuits and eases the system-level design of the driving amplifier, anti-aliasing filter, and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. An integrated low-noise voltage reference eases board level design without requiring external decoupling capacitors. The output digital data is provided through a JESD204B subclass 1 interface from a 56-pin, 8-mm × 8-mm WQFN package. A SPI is available to configure the device that is compatible with 1.2-V to 3-V logic.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC16DX370 | WQFN (56) | 8.00 × 8.00 mm |
SPACE
Changes from B Revision (April 2014) to C Revision
Changes from A Revision (April 2014) to B Revision
Changes from * Revision (April 2014) to A Revision
PIN | TYPE OR DIAGRAM | DESCRIPTION | |
---|---|---|---|
NAME | NUMBER | ||
AGND | 3, 6, 9, 12, 16, 19, 22, 31, 40, 49, 52, 55 | Analog ground | Analog ground Must be connected to a solid ground reference plane under the device. |
BP2.5 | 41 | Bypass pins | Capacitive bypassing pin for internally regulated 2.5-V supply This pin must be decoupled to AGND with a 0.1-μF and a 10-µF capacitor located close to the pin. |
CLKIN+, CLKIN– | 17, 18 |
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Differential device clock input pins Each pin is internally terminated to a DC bias with a 50-Ω resistor for a 100-Ω total internal differential termination. AC coupling is required for coupling the clock input to these pins if the clock driver cannot meet the common-mode requirements. Sampling occurs on the rising edge of the differential signal (CLKIN+) − (CLKIN–). |
CSB | 54 |
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SPI chip select pin When this signal is asserted, SCLK is used to clock the input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is high impedance and the input data is ignored. Active low. A 10 kΩ pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2- to 3.0-V CMOS logic levels. |
DGND | 25, 46 | Digital ground | Digital ground Must be connected to the same solid ground reference plane under the device to which AGND connects. Bypass capacitors connected to the VD1.2 pins must be connected to ground as close to this DGND pins as possible. |
OVRA, OVRB | 44, 43 |
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Over-range detection outputs These pins output the channel A and channel B over-range signals as 1.8-V CMOS logic level outputs. |
SA0+, SA0–, SA1+, SA1– | 38, 39, 36, 37 |
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Differential high speed serial data lane pins for channel A These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100-Ω characteristic impedance. In single-lane mode, SA0+ or SAO– is used to transfer data and SA1+ or SA1– is undefined and may be left floating. |
SB0+, SB0–, SB1+, SB1– | 32, 33, 34, 35 | Differential high speed serial data lane pins for channel B. These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100-Ω characteristic impedance. In single-lane mode, SB0+ or SB0– is used to transfer data and SB1+ and SB1– is undefined and may be left floating. | |
SCLK | 53 |
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SPI serial clock pin Serial data is shifted into and out of the device synchronous with this clock signal. Compatible with 1.2- to 3.0-V CMOS logic levels. |
SDI | 47 | SPI data input pin Serial data is shifted into the device on this pin while the CSB signal is asserted. Compatible with 1.2- to 3.0-V CMOS logic levels. |
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SDO | 48 |
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SPI data output pin Serial data is shifted out of the device on this pin during a read command while CSB is asserted. The output logic level is configurable as 1.2, 1.8, 2.5, or 3.0 V. The output level must be configured after power up and before performing a read command. See the Register Descriptions for configuration details. |
SYNCb+, SYNCb– | 27, 28 |
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Differential SYNCb signal input pins DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100-Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common-mode range. The SYNCb signal is active low and therefore asserted when the voltage at SYNCb+ is less than at SYNCb–. |
SYSREF+, SYSREF– | 23, 24 |
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Differential SYSREF signal input pins Each pin is internally terminated to a DC bias with a 1-kΩ resistor. An external 100-Ω differential termination must always be provided. AC coupling using capacitors is required for coupling the SYSREF signal to these pins if the clock driver cannot meet the common-mode requirements. In the case of AC coupling, the termination must be placed on the source side of the coupling capacitors. |
VA1.2 | 8, 21, 30, 50 | Supply input pin | 1.2-V analog power supply pins These pins must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin. |
VA1.8 | 7, 15, 20, 29, 51, 56 | Supply input pin | 1.8-V analog power supply pins These pins must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin. |
VA3.0 | 2, 13, 42 | Supply input pin | 3.0-V analog power supply pin This pin must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to the pin. |
VCMA, VCMB | 1, 14 |
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Input interface common mode voltage for channels A and B These pins must be bypassed to AGND with low equivalent series inductance (ESL) 0.1-μF capacitors. One capacitor should be placed as close to the pin as possible and additional capacitors placed at the bias load points. 10-μF capacitors should also be placed in parallel. TI recommends to use VCMA and VCMB to provide the common mode voltage for the differential analog inputs. The input common mode bias is provided internally for the ADC input; therefore, external use of VCMA and VCMB is recommended, but not strictly required. The recommended bypass capacitors are always required. |
VD1.2 | 26, 45 | Supply input pin | 1.2-V digital power supply pin This pin must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin. |
VINA+, VINA– | 4, 5 |
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Differential analog input pins of channel A Each input pin is terminated to the internal common mode reference with a resistor for an internal differential termination. |
VINB+, VINB– | 11, 10 | Differential analog input pins of channel B Each input pin is terminated to the internal common mode reference with a resistor for an internal differential termination. |
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0 | Exposed thermal pad | Exposed thermal pad The exposed pad must be connected to the AGND ground plane electrically and with good thermal dissipation properties to achieve rated performance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage: VA3.0 | –0.3 | 4.2 | V | |
Supply Voltage: VA1.8 | –0.3 | 2.35 | V | |
Supply Voltage: VA1.2, VD1.2 | –0.3 | 1.55 | V | |
Voltage at VINA+, VINA– | VCMA – 1.0 | VCMA + 0.75 | V | |
Voltage at VINB+, VINB– | VCMB – 1.0 | VCMB + 0.75 | V | |
Voltage at VCMA, VCMB | –0.3 | VA3.0 + 0.3, not to exceed 4.2 V | V | |
Voltage at OVRA, ORVB | –0.3 | VA1.8 + 0.3 | V | |
Voltage at SCLK, SDI, CSb | –0.3 | VA3.0 + 0.3, not to exceed 4.2 V | V | |
Voltage at SDO | –0.3 | VSPI + 0.3, not to exceed 4.2 V | V | |
Voltage at CLKIN+, CLKIN–, SYSREF+, SYSREF– | –0.3 | 1.55 | V | |
Voltage at SYNC+, SYNC– | –0.3 | VBP2.5 + 0.3 | V | |
Voltage at BP2.5 | –0.3 | 3.2 | V | |
Voltage at SA0+, SA0–, SA1+, SA1–, SB0+, SB0–, SB1+, SB1– | –0.3 | VBP2.5 + 0.3 | V | |
Input current at any pin(3) | 5 | mA | ||
TJ | Operating junction temperature(2) | 125 | °C |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | –65 | 150 | °C | |
V(ESD)(1) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) | –1000 | 1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) | –250 | 250 | V |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Specified temperature | –40 | 85 | °C | |
VA3.0 | 3.0-V analog supply voltage | 2.85 | 3.45 | V |
VA1.8 | 1.8-V analog supply voltage | 1.7 | 1.9 | V |
VA1.2 | 1.2-V analog supply voltage | 1.15 | 1.25 | V |
VD1.2 | 1.2-V digital supply voltage | 1.15 | 1.25 | V |
CLKIN duty cycle | 30% | 70% | ||
TJ | Operating junction temperature | 105 | °C |
THERMAL METRIC(1) | WQFN (56 PINS) | UNIT | |
---|---|---|---|
RθJA | Thermal resistance, junction to ambient | 24.9 | °C/W |
RθJC(top) | Thermal resistance, junction to package top | 8.6 | |
RθJB | Thermal resistance, junction to board | 3.0 | |
φJT | Characterization parameter, junction to package top | 0.2 | |
φJB | Characterization parameter, junction to board | 2.9 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IA3.0 | VA3.0 supply current consumption | Normal operation, single data lane per channel | 230 | mA | |||
Normal operation, dual data lane per channel | 255 | ||||||
Power down mode | 8.7 | ||||||
IA1.8 | VA1.8 supply current consumption | Normal operation | 360 | mA | |||
Power down mode | 3.6 | ||||||
IA1.2 | VA1.2 supply current consumption | Normal operation | 172 | mA | |||
Power down mode | 3.3 | ||||||
ID1.2 | VD1.2 supply current consumption | Normal operation | 52 | mA | |||
Power down mode | 3.3 | ||||||
PT | Total power consumption of the VA3.0 , VA1.8 , VA1.2 , VD1.2 supplies |
Normal operation, single serial lane per channel | TA = 25°C | 1607 | mW | ||
TA = TMIN to TMAX | 1800 | ||||||
Power consumption during power-down state, external clock active | 30 | ||||||
Power consumption during sleep state, external clock active | 30 | ||||||
VBP2.5 | Voltage at the BP2.5 pin | 2.65 | V | ||||
Supply sensitivity to noise Power of spectral spur resulting from a 100-mV sinusoidal signal modulating a supply at 500 kHz. Analog input is a –3 dBFS 150-MHz single tone. In all cases, the spur appears as part of a pair symmetric about the fundamental that scales proportionally with the fundamental amplitude. |
dBFS | ||||||
VA3.0 | –72.5 | ||||||
VA1.8 | –58.0 | ||||||
VA1.2 | –37.7 | ||||||
VD1.2 | –78 |
PARAMETER | DESCRIPTION AND TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
FSR | Full scale range Differential peak-to-peak |
1.7 | Vpp | ||||
GVAR | Gain variation Variation of input voltage to output code gain between different parts, part-to-part or channel-to-channel |
±0.07 | dB | ||||
VOFF | Input referred voltage offset | ±13 | mV | ||||
BW3dB | 3-dB bandwidth Frequency at which the voltage input to digital output response deviates by 3 dB compared to low frequencies for a low impedance differential signal applied at the input pins. Includes 0.5-nH parasitic inductance in series with each pin of the differential analog input. |
800 | MHz | ||||
RIN | Input termination resistance Differential |
200 | Ω | ||||
CIN | Input capacitance, differential | 3.7 | pF | ||||
VCMA, VCMB | Input common mode voltage reference voltage at the VCMA or VCMB pins Varies with temperature |
1.6 | V | ||||
IVCM | Input common mode voltage reference current sourcing or sinking on VCMA or VCMB pins | 1 | mA | ||||
VCM-OFF | Input common mode voltage offset range Allowable difference between the common mode applied to the analog input of a particular channel and the bias voltage at the respective common mode VCM bias pin (VCMA or VCMB) |
±50 | mV |
PARAMETER | DESCRIPTION AND TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUT CHARACTERISTICS (CLKIN) | ||||||
VID | Input differential voltage(1)(3)
Differential peak voltage |
250 | 1000 | mV | ||
dVSS/dt | Recommended minimum edge slew rate at the zero crossing(1)
|
2 | 5 | V/ns | ||
VIS-BIAS | Input offset voltage internal bias (1)
Internally biased |
0.5 | V | |||
VIS-IN | Externally applied input offset voltage(3)
Allowable common mode voltage range for DC coupled interfaces |
0.4 | 0.5 | 0.6 | V | |
Zrdiff | Differential termination resistance at DC(2) | 130 | Ω | |||
Ztt | Common-mode bias source impedance(2) | 11 | kΩ | |||
CT | Differential termination capacitance | 1.5 | pF | |||
DIGITAL INPUT CHARACTERISTICS (SYSREF) | ||||||
VID | Input differential voltage (1)(3)
Differential peak voltage |
250 | 1000 | mV | ||
VIS-BIAS | Input offset voltage bias (1)
Internally biased |
0.5 | V | |||
VIS-IN | Externally applied input offset voltage(3)
Allowable common mode voltage range for DC coupled interfaces |
0.4 | 0.5 | 0.6 | V | |
Zrdiff | Differential termination resistance at DC(2) | 2 | kΩ | |||
Ztt | Common-mode bias source impedance(2) | 11 | kΩ | |||
CT | Differential termination capacitance(2) | 0.8 | pF | |||
DIGITAL INPUT CHARACTERISTICS (SYNCb) | ||||||
VID | Input differential voltage (1)(3)
Differential peak voltage |
350 | mV | |||
VIS-IN | Externally applied input offset voltage(1)(3) | 0.5 | 1.2 | 2 | V | |
Zrdiff | Differential termination resistance(2) | 100 | Ω | |||
CT | Differential termination capacitance(2) | 1 | pF |
PARAMETER | DESCRIPTION AND TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SERIAL LANE OUTPUT CHARACTERISTICS (SA0, SA1, SB0, SB1) | ||||||
VOD | Output differential voltage(1)
Differential peak-peak values. Assumes ideal 100-Ω load. De-emphasis disabled. Configurable via SPI |
580 680 760 860 960 1060 1140 1240 |
mV | |||
Zddiff | Differential output impedance at DC(2) | 100 | Ω | |||
RLddiff | Differential output return loss magnitude Relative to 100 Ω; For frequencies up to 5.5 GHz |
–11 | dB | |||
Rdeemp | Transmitter de-emphasis values VOD configured to default value. |
0 0.4 1.2 2.1 2.8 3.8 4.8 6.8 |
dB |
PARAMETER | DESCRIPTION AND TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUT CHARACTERISTICS (SDI, SCLK, CSB) | ||||||
VIH | Logical 1 input voltage(1)
Inputs are compatible with 1.2-V up to 3.0-V logic. |
0.9 | V | |||
VIL | Logical 0 input voltage(1) | 0.3 | V | |||
IIN0 | Logic low input current | 0.5 | uA | |||
IIN1 | Logic high input current | 0.5 | uA | |||
CIN | Input capacitance | 2 | pF | |||
DIGITAL OUTPUT CHARACTERISTICS (SDO) | ||||||
VOH | Logical 1 output voltage(1)(2)
VSPI = 1.2, 1.8, 2.5, or 3 V ; Configurable via SPI |
VSPI – 0.3 | VSPI(2) | V | ||
VOL | Logical 0 output voltage(1)(2) | 0 | 0.3 | V | ||
+ISC | Logic high short circuit current | 9 | mA | |||
–ISC | Logic low short circuit current | –10 | mA | |||
DIGITAL OUTPUT CHARACTERISTICS (OVRA/TRIGRDY, OVRB) | ||||||
VOH | Logical 1 output voltage(1) | 1.5 | 1.8 | V | ||
VOL | Logical 0 output voltage(1) | 0 | 0.3 | V | ||
+ISC | Logic high short circuit current | 17.7 | mA | |||
–ISC | Logic low short circuit current | –15 | mA | |||
DIGITAL INPUT CHARACTERISTICS (TRIGGER) | ||||||
VIH | Logical 1 input voltage(1) | 1.5 | V | |||
VIL | Logical 0 input voltage(1) | 0.3 | V | |||
IIN0 | Logic low input current | 0.5 | uA | |||
IIN1 | Logic high input current | 0.5 | uA | |||
CIN | Input capacitance | 3 | pF |
PARAMETER | DESCRIPTION | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ADC SAMPLING INSTANT TIMING CHARACTERISTICS | ||||||
FS | Sampling rate Equal to FCLKIN / CLKDIV |
50 | 370 | MSPS | ||
FCLKIN | Input Clock Frequency at CLKIN Inputs | MHz | ||||
CLKDIV = 1 | 50 | 370 | ||||
CLKDIV = 2 | 100 | 740 | ||||
CLKDIV = 4 | 200 | 1480 | ||||
CLKDIV = 8 | 400 | 2000 | ||||
tLAT-ADC | ADC core latency Delay from a reference sampling instant to the boundary of the internal LMFC where the reference sample is the first sample of the next transmitted multi-frame. Coarse sampling phase adjust disabled. In this device, the frame clock period is equal to the sampling clock period. |
12.5 | Frame clock cycles | |||
tJ | Additive sampling aperture jitter Depends on input CLKIN differential edge rate at the zero crossing, dVSS/dt. Tested with 5 V/ns edge rate. |
fs | ||||
CLKDIV = 1 | 70 | |||||
CLKDIV = 2, 4, coarse phase disabled | 80 | |||||
CLKDIV = 4, coarse phase enabled. Typical worst-case value across all coarse phase configuration possibilities. | 85 | |||||
OVER-RANGE INTERFACE TIMING CHARACTERISTICS (OVRA, OVRB) | ||||||
tODH | OVR assertion delay Delay between an over-range value sampled and OVR asserted; Coarse clock phase adjust disabled. |
7.5 | Frame clock cycles | |||
tODL | OVR de-assertion delay Delay between first under-range value sampled until OVR de-assertion; Configurable via SPI. |
tODH + 0 | tODH + 15 | Frame clock cycles | ||
SYSREF TIMING CHARACTERISTICS | ||||||
tPH-SYS | SYSREF assertion duration Required duration of SYSREF assertion after rising edge event |
2 | Frame clock cycles | |||
tPL-SYS | SYSREF de-assertion duration Required duration of SYSREF de-assertion after falling edge event |
2 | Frame clock cycles | |||
tS-SYS | SYSREF setup time Relative to CLKIN rising edge |
320 | ps | |||
tH-SYS | SYSREF hold time Relative to CLKIN rising edge |
80 | ps | |||
JESD204B INTERFACE LINK TIMING CHARACTERISTICS | ||||||
tD-LMFC | SYSREF to LMFC delay Functional delay between SYSREF assertion latched and LMFC frame boundary. Depends on CLKDIV setting. |
CLKIN cycles (Frame clock cycles) |
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CLKDIV = 1 | 3.5 (3.5) |
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CLKDIV = 2 | 8 (4) |
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CLKDIV = 4 | 15 (3.75) |
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CLKDIV = 8 | 29 (3.625) |
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tD-K28 | LMFC to K28.5 delay Functional delay between the start of the first K28.5 frame during Code Group Synchronization at the serial output and the preceding LMFC frame boundary. |
5 | 6 | 7 | Frame clock cycles | |
tD-ILA | LMFC to ILA delay Functional delay between the start of the first ILA frame during Initial Lane Synchronization at the serial output and the preceding LMFC frame boundary |
5 | 6 | 7 | ||
tD-DATA | LMFC to valid data delay Functional delay between the start of the first valid data frame at the serial output and the preceding LMFC frame boundary. |
5 | 6 | 7 | ||
tS-SYNCb-F | SYNCb setup time Required SYNCb setup time relative to the internal LMFC boundary. |
3 | Frame clock cycles | |||
tH-SYNCb-F | SYNCb hold time Required SYNCb hold time relative to the internal LMFC boundary . |
0 | ||||
tH-SYNCb | SYNCb assertion hold time Required SYNCb hold time after assertion before de-assertion to initiate a link re-synchronization. |
4 | ||||
tILA | ILA duration Duration of the ILA sequence . |
4 | Multi-frame clock cycles | |||
SERIAL OUTPUT DATA TIMING CHARACTERISTICS | ||||||
FSR | Serial bit rate Single- or dual-lane mode |
1 | 7.4 | Gb/s | ||
UI | Unit Interval 7.4 Gb/s Data Rate |
135.1 | ps | |||
DJ | Deterministic jitter Includes periodic jitter (PJ), data dependent jitter (DDJ), duty cycle distortion (DCD), and inter-symbol interference (ISI); 7.4 Gb/s data rate. |
0.047 (6.33) |
p-p UI (p-p ps) |
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RJ | Random jitter Assumes BER of 1e-15 (Q = 15.88); 7.4 Gb/s data rate |
0.156 (1.35) |
p-p UI (rms ps) |
|||
TJ | Total jitter Sum of DJ and RJ. Assumes BER of 1e-15 (Q = 15.88); 7.4 Gb/s data rate. |
0.206 (27.77) |
p-p UI (p-p ps) |
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SPI BUS TIMING CHARACTERISTICS(1) | ||||||
ƒSCLK | Serial clock frequency fSCLK = 1 / tP |
20 | MHz | |||
tPH | SCLK pulse width – high % of SCLK period |
25% | 75% | |||
tPL | SCLK pulse width – low % of SCLK period |
25% | 75% | |||
tSSU | SDI input data setup time | 5 | ns | |||
tSH | SDI input data hold time | 5 | ns | |||
tODZ | SDO output data driven-to-3-state time | 25 | ns | |||
tOZD | SDO output data 3-state-to-driven time | 25 | ns | |||
tOD | SDO output data delay time | 30 | ns | |||
tCSS | CSB setup time | 5 | ns | |||
tCSH | CSB hold time | 5 | ns | |||
tIAG | Inter-access gap Minimum time CSB must be de-asserted between accesses |
5 | ns |
For more information, see Functional Block Diagram.
SNR = 68.49 dBFS | SFDR = 83.21 dBFS | |
Nominal Supplies: | VA3.0 = 3.0 V | VA1.2 = VD1.2 = 1.2 V |
VA1.8 = 1.8 V |
Nominal Supplies: | VA3.0 = 3.0 V | VA1.2 = VD1.2 = 1.2 V |
VA1.8 = 1.8 V |
SNR = 69.5 dBFS | SFDR = 87.0 dBFS |
SNR = 69.5 dBFS | SFDR = 94 dBFS | IMD3 = –100 dBFS |