The ADC31RF80 device is a 14-bit, 3-GSPS, single-channel telecom receiver and feedback device that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC31RF80 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
The ADC31RF80 comes with a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC31RF80 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC31RF80 | VQFN (72) | 10.00 mm × 10.00 mm |
DATE | REVISION | NOTES |
---|---|---|
August 2017 | * | Initial release. |
NAME | NO. | I/O | DESCRIPTION |
---|---|---|---|
INPUT, REFERENCE | |||
INM | 41 | I | Differential analog input |
INP | 42 | ||
CM | 22 | O | Common-mode voltage for analog inputs, 1.2 V |
NC | 1, 2, 13, 14, 65, 66, 68, 69, 71, 72 | — | Do not connect these pins. |
CLOCK, SYNC | |||
CLKINM | 28 | I | Differential clock input for the analog-to-digital converter (ADC). This pin has an internal differential 100-Ω termination. |
CLKINP | 27 | ||
SYSREFM | 34 | I | External SYSREF input. This pin has an internal, differential 100-Ω termination and requires external biasing. |
SYSREFP | 33 | ||
GPIO1 | 19 | I/O | GPIO control pin; configured through the SPI. This pin can be configured to be either a fast overrange output, a fast detect alarm signal from the peak power detect, or a numerically-controlled oscillator (NCO) control. GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input. |
GPIO2 | 20 | ||
GPIO3 | 21 | ||
GPIO4 | 63 | ||
CONTROL, SERIAL | |||
RESET | 48 | I | Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor. |
SCLK | 6 | I | Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor. |
SDIN | 5 | I/O | Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN can be data input in 4-wire mode, data input and output in 3 wire-mode. |
SEN | 7 | I | Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD. |
SDOUT | 11 | O | Serial interface data output in 4-wire mode |
PDN | 50 | I | Power down; active high. This pin has an internal 20-kΩ pulldown resistor. |
DATA INTERFACE | |||
D0M | 62 | O | JESD204B serial data output |
D0P | 61 | ||
D1M | 59 | ||
D1P | 58 | ||
D2M | 56 | ||
D2P | 55 | ||
D3M | 54 | ||
D3P | 53 | ||
SYNCBM | 36 | I | Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic input, an optional on-chip 100-Ω termination, and is selectable through the SPI. This pin requires external biasing. |
SYNCBP | 35 | ||
POWER SUPPLY | |||
AVDD19 | 10, 16, 24, 31, 39, 45 | I | Analog 1.9-V power supply |
AVDD | 9, 12, 15, 17, 25, 30, 38, 40, 43, 44, 46 | I | Analog 1.15-V power supply |
DVDD | 4, 8, 47, 51, 57, 64, 70 | I | Digital 1.15 V-power supply, including the JESD204B transmitter |
GND | 3, 18, 23, 26, 29, 32, 37, 49, 52, 60, 67 | I | Ground; shorted to thermal pad inside device |