SBAS671C July   2014  – March 2016 ADC3241 , ADC3242 , ADC3243 , ADC3244

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADC3241, ADC3242
    6. 7.6  Electrical Characteristics: ADC3243, ADC3244
    7. 7.7  Electrical Characteristics: General
    8. 7.8  AC Performance: ADC3241
    9. 7.9  AC Performance: ADC3242
    10. 7.10 AC Performance: ADC3243
    11. 7.11 AC Performance: ADC3244
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3241
    16. 7.16 Typical Characteristics: ADC3242
    17. 7.17 Typical Characteristics: ADC3243
    18. 7.18 Typical Characteristics: ADC3244
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 14x Serialization
        2. 9.3.3.2 Two-Wire Interface: 7x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
        1. 9.4.3.1 Improving Wake-Up Time From Global Power-Down
      4. 9.4.4 Internal Dither Algorithm
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Description
        1. 9.6.2.1  Register 01h
        2. 9.6.2.2  Register 03h
        3. 9.6.2.3  Register 04h
        4. 9.6.2.4  Register 05h
        5. 9.6.2.5  Register 06h
        6. 9.6.2.6  Register 07h
        7. 9.6.2.7  Register 09h
        8. 9.6.2.8  Register 0Ah
        9. 9.6.2.9  Register 0Bh
        10. 9.6.2.10 Register 0Eh
        11. 9.6.2.11 Register 0Fh
        12. 9.6.2.12 Register 13h (address = 13h)
        13. 9.6.2.13 Register 15h
        14. 9.6.2.14 Register 25h
        15. 9.6.2.15 Register 27h
        16. 9.6.2.16 Register 41Dh
        17. 9.6.2.17 Register 422h
        18. 9.6.2.18 Register 434h
        19. 9.6.2.19 Register 439h
        20. 9.6.2.20 Register 51Dh
        21. 9.6.2.21 Register 522h
        22. 9.6.2.22 Register 534h
        23. 9.6.2.23 Register 539h
        24. 9.6.2.24 Register 608h
        25. 9.6.2.25 Register 70Ah
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

The ADC324x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 184. Some important points to remember during laying out the board are:

  1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions, as shown in the reference layout of Figure 184 as much as possible.
  2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 184 as much as possible.
  3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, do not keep the digital output traces parallel to the analog input traces because this configuration can result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched in length to avoid skew among outputs.
  4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source.

12.2 Layout Example

ADC3241 ADC3242 ADC3243 ADC3244 Lyt_BAS671.gif Figure 184. Typical Layout of the ADC324x Board