The ADC32J2x is a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC32J2X | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from * Revision (May 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 4, 5, 8, 9, 12, 17, 20, 25, 28, 29, 32, 39, 46 | I | Analog 1.8-V power supply |
CLKM | 18 | I | Negative differential clock input for the ADC |
CLKP | 19 | I | Positive differential clock input for the ADC |
DAM | 48 | O | Negative serial JESD204B output for channel A |
DAP | 47 | O | Positive serial JESD204B output for channel A |
DBM | 45 | O | Negative serial JESD204B output for channel B |
DBP | 44 | O | Positive serial JESD204B output for channel B |
DVDD | 3,34 | I | Digital 1.8-V power supply |
GND | PowerPAD™ | I | Ground, 0 V |
INAM | 11 | I | Negative differential analog input for channel A |
INAP | 10 | I | Positive differential analog input for channel A |
INBM | 26 | I | Negative differential analog input for channel B |
INBP | 27 | I | Positive differential analog input for channel B |
NC | 2, 6, 7, 30, 31, 35, 37, 38, 40, 41 | — | Do not connect |
OVRA | 1 | O | Overrange indicator for channel A |
OVRB | 36 | O | Overrange indicator for channel B |
PDN | 33 | I | Power-down control. This pin has an internal 150-kΩ pulldown resistor. |
RESET | 21 | I | Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. |
SCLK | 13 | I | Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. |
SDATA | 14 | I | Serial Interface data input. This pin has an internal 150-kΩ pulldown resistor. |
SDOUT | 16 | O | Serial interface data output |
SEN | 15 | I | Serial interface enable; active low. This pin has an internal 150-kΩ pullup resistor to AVDD. |
SYNCM~ | 42 | I | Positive JESD204B synch input |
SYNCP~ | 43 | I | Negative JESD204B synch input |
SYSREFM | 23 | I | Negative external SYSREF input |
SYSREFP | 22 | I | Positive external SYSREF input |
VCM | 24 | O | Common-mode voltage output for analog inputs |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage range, AVDD | –0.3 | 2.1 | V | |
Supply voltage range, DVDD | –0.3 | 2.1 | V | |
Voltage applied to input pins: | INAP, INBP | –0.3 | AVDD + 0.3 | V |
CLKP, CLKM | –0.3 | AVDD + 0.3 | V | |
SYSREFP, SYSREFM, SYNCP~, SYNCM~ | –0.3 | AVDD + 0.3 | V | |
SCLK, SEN, SDATA, RESET, PDN | –0.3 | AVDD + 0.3 | V | |
Temperature range | Operating free-air, TA | –40 | 85 | °C |
Operating junction, TJ | 125 | °C | ||
Storage, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLIES | ||||||
AVDD | Analog supply voltage range | 1.7 | 1.8 | 1.9 | V | |
DVDD | Digital supply voltage range | 1.7 | 1.8 | 1.9 | V | |
ANALOG INPUT | ||||||
VID | Differential input voltage | For input frequencies < 450 MHz | 2 | VPP | ||
For input frequencies < 600 MHz | 1 | VPP | ||||
VIC | Input common-mode voltage | VCM ± 0.025 | V | |||
CLOCK INPUT | ||||||
Input clock frequency | Sampling clock frequency | 25 | 160(1) | MSPS | ||
Input clock amplitude (differential) | Sine wave, ac-coupled | 1.5 | V | |||
LPECL, ac-coupled | 1.6 | V | ||||
LVDS, ac-coupled | 0.7 | V | ||||
Input clock duty cycle | 50% | |||||
Input clock common-mode voltage | 0.95 | V | ||||
DIGITAL OUTPUTS | ||||||
CLOAD | Maximum external load capacitance from each output pin to GND | 3.3 | pF | |||
RLOAD | Single-ended load resistance | 100 | Ω |
THERMAL METRIC(1) | ADC32J2x | UNIT | |
---|---|---|---|
RGZ (VQFN) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 25.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 3.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Differential input full-scale | 2.0 | VPP | ||||
Input resistance | Differential at dc | 6.5 | kΩ | |||
Input capacitance | Differential at dc | 5.2 | pF | |||
VCM common-mode voltage output | 0.95 | V | ||||
VCM output current capability | 10 | mA | ||||
Input common-mode current | Per analog input pin | 1.5 | µA/MSPS | |||
Analog input bandwidth (3 dB) | 50-Ω differential source driving 50-Ω termination across INP and INM | 450 | MHz | |||
DC ACCURACY | ||||||
Offset error | –20 | 20 | mV | |||
EG(REF) | Gain error as a result of internal reference inaccuracy alone | –3 | 3 | %FS | ||
EG(CHAN) | Gain error of channel alone | ±1 | %FS | |||
Temperature coefficient of EG(CHAN) | –0.017 | Δ%FS/°C | ||||
CHANNEL-TO-CHANNEL ISOLATION | ||||||
Crosstalk | fIN = 10 MHz | 105 | dB | |||
fIN = 100 MHz | 105 | dB | ||||
fIN = 200 MHz | 105 | dB | ||||
fIN = 230 MHz | 105 | dB | ||||
fIN = 300 MHz | 105 | dB |
PARAMETER | ADC32J22 | ADC32J23 | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||
ADC clock frequency | 50 | 80 | MSPS | |||||
Resolution | 12 | 12 | Bits | |||||
1.8-V analog supply current | 134 | 267 | 152 | 272 | mA | |||
1.8-V digital supply current | 22 | 40 | 31 | 46 | mA | |||
Total power dissipation | 281 | 435 | 329 | 450 | mW | |||
Global power-down dissipation | 5 | 5 | mW | |||||
Wake-up time from global power-down | 85 | 85 | µs | |||||
Standby power-down dissipation | 99 | 105 | mW | |||||
Wake-up time from standby power-down | 35 | 35 | µs |
PARAMETER | ADC32J24 | ADC32J25 | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||
ADC clock frequency | 125 | 160 | MSPS | |||||
Resolution | 12 | 12 | Bits | |||||
1.8-V analog supply current | 177 | 292 | 192 | 302 | mA | |||
1.8-V digital supply current | 46 | 65 | 56 | 80 | mA | |||
Total power dissipation | 401 | 535 | 454 | 560 | mW | |||
Global power-down dissipation | 5 | 5 | mW | |||||
Wake-up time from global power-down | 85 | 85 | µs | |||||
Standby power-down dissipation | 112 | 118 | mW | |||||
Wake-up time from standby power-down | 35 | 35 | µs |
PARAMETER | TEST CONDITIONS | ADC32J25 (fS = 160 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
DYNAMIC AC CHARACTERISTICS | |||||||||
SNR | Signal-to-noise ratio | fIN = 10 MHz | 70.3 | 70.5 | dBFS | ||||
fIN = 70 MHz | 68 | 69.8 | 70.0 | ||||||
fIN = 100 MHz | 69.5 | 69.7 | |||||||
fIN = 170 MHz | 68.6 | 69.1 | |||||||
fIN = 230 MHz | 67.8 | 68.3 | |||||||
NSD | Noise spectral density (averaged across Nyquist zone) |
fIN = 10 MHz | 149.3 | 149.5 | dBFS/Hz | ||||
fIN = 70 MHz | –147.5 | 148.8 | 149.0 | ||||||
fIN = 100 MHz | 148.5 | 148.7 | |||||||
fIN = 170 MHz | 147.7 | 148.1 | |||||||
fIN = 230 MHz | 146.8 | 147.3 | |||||||
SINAD | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.2 | 70.4 | dBFS | ||||
fIN = 70 MHz | 67.3 | 69.7 | 69.9 | ||||||
fIN = 100 MHz | 69.4 | 68.8 | |||||||
fIN = 170 MHz | 68.4 | 68.8 | |||||||
fIN = 230 MHz | 67.5 | 67.8 | |||||||
ENOB | Effective number of bits | fIN = 10 MHz | 11.4 | 11.4 | Bits | ||||
fIN = 70 MHz | 10.9 | 11.3 | 11.3 | ||||||
fIN = 100 MHz | 11.2 | 11.3 | |||||||
fIN = 170 MHz | 11.1 | 11.1 | |||||||
fIN = 230 MHz | 10.9 | 10.9 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 91 | 88 | dBc | ||||
fIN = 70 MHz | 78 | 86 | 85 | ||||||
fIN = 100 MHz | 85 | 84 | |||||||
fIN = 170 MHz | 83 | 82 | |||||||
fIN = 230 MHz | 81 | 80 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 91 | 92 | dBc | ||||
fIN = 70 MHz | 78 | 93 | 93 | ||||||
fIN = 100 MHz | 92 | 93 | |||||||
fIN = 170 MHz | 83 | 82 | |||||||
fIN = 230 MHz | 81 | 80 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 91 | 88 | dBc | ||||
fIN = 70 MHz | 78 | 86 | 85 | ||||||
fIN = 100 MHz | 85 | 84 | |||||||
fIN = 170 MHz | 91 | 87 | |||||||
fIN = 230 MHz | 87 | 87 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 99 | 95 | dBc | ||||
fIN = 70 MHz | 87 | 98 | 94 | ||||||
fIN = 100 MHz | 96 | 94 | |||||||
fIN = 170 MHz | 91 | 90 | |||||||
fIN = 230 MHz | 91 | 89 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 87 | 85 | dBc | ||||
fIN = 70 MHz | 75 | 84 | 83 | ||||||
fIN = 100 MHz | 83 | 82 | |||||||
fIN = 170 MHz | 81 | 80 | |||||||
fIN = 230 MHz | 78 | 77 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
91 | 91 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
86 | 86 | |||||||
DNL | Differential nonlinearity | fIN = 70 MHz | ±0.1 | ±0.1 | LSBs | ||||
INL | Integrated nonlinearity | fIN = 70 MHz | ±0.4 | ±0.4 | LSBs |
PARAMETER | TEST CONDITIONS | ADC32J24 (fS = 125 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
DYNAMIC AC CHARACTERISTICS | |||||||||
SNR | Signal-to-noise ratio | fIN = 10 MHz | 70.3 | 70.5 | dBFS | ||||
fIN = 70 MHz | 68.8 | 70.1 | 70.3 | ||||||
fIN = 100 MHz | 70.1 | 70.2 | |||||||
fIN = 170 MHz | 69.4 | 69.8 | |||||||
fIN = 230 MHz | 68.7 | 69.2 | |||||||
NSD | Noise spectral density (averaged across Nyquist zone) |
fIN = 10 MHz | 148.3 | 148.5 | dBFS/Hz | ||||
fIN = 70 MHz | –146.8 | 148.1 | 148.3 | ||||||
fIN = 100 MHz | 148.0 | 148.2 | |||||||
fIN = 170 MHz | 147.3 | 147.8 | |||||||
fIN = 230 MHz | 146.7 | 147.2 | |||||||
SINAD | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.3 | 70.4 | dBFS | ||||
fIN = 70 MHz | 67.6 | 70.1 | 70.3 | ||||||
fIN = 100 MHz | 70.0 | 70.1 | |||||||
fIN = 170 MHz | 69.2 | 69.6 | |||||||
fIN = 230 MHz | 68.3 | 68.8 | |||||||
ENOB | Effective number of bits | fIN = 10 MHz | 11.4 | 11.4 | Bits | ||||
fIN = 70 MHz | 11 | 11.4 | 11.4 | ||||||
fIN = 100 MHz | 11.3 | 11.4 | |||||||
fIN = 170 MHz | 11.2 | 11.3 | |||||||
fIN = 230 MHz | 11.1 | 11.1 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 93 | 92 | dBc | ||||
fIN = 70 MHz | 78.5 | 91 | 90 | ||||||
fIN = 100 MHz | 90 | 90 | |||||||
fIN = 170 MHz | 85 | 84 | |||||||
fIN = 230 MHz | 82 | 81 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 93 | 92 | dBc | ||||
fIN = 70 MHz | 78.5 | 91 | 90 | ||||||
fIN = 100 MHz | 90 | 90 | |||||||
fIN = 170 MHz | 85 | 84 | |||||||
fIN = 230 MHz | 82 | 81 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 96 | 92 | dBc | ||||
fIN = 70 MHz | 80 | 95 | 90 | ||||||
fIN = 100 MHz | 95 | 92 | |||||||
fIN = 170 MHz | 88 | 86 | |||||||
fIN = 230 MHz | 90 | 93 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 98 | 96 | dBc | ||||
fIN = 70 MHz | 87 | 99 | 95 | ||||||
fIN = 100 MHz | 97 | 96 | |||||||
fIN = 170 MHz | 97 | 94 | |||||||
fIN = 230 MHz | 96 | 91 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 91 | 88 | dBc | ||||
fIN = 70 MHz | 75 | 89 | 87 | ||||||
fIN = 100 MHz | 88 | 88 | |||||||
fIN = 170 MHz | 83 | 82 | |||||||
fIN = 230 MHz | 80 | 79 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
91 | 91 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
86 | 86 | |||||||
DNL | Differential nonlinearity | fIN = 70 MHz | ±0.1 | ±0.1 | LSBs | ||||
INL | Integrated nonlinearity | fIN = 70 MHz | ±0.4 | ±0.4 | LSBs |
PARAMETER | TEST CONDITIONS | ADC32J23 (fS = 80 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
DYNAMIC AC CHARACTERISTICS | |||||||||
SNR | Signal-to-noise ratio | fIN = 10 MHz | 70.3 | 70.4 | dBFS | ||||
fIN = 70 MHz | 68.7 | 70.1 | 70.2 | ||||||
fIN = 100 MHz | 70.0 | 70.2 | |||||||
fIN = 170 MHz | 69.6 | 69.9 | |||||||
fIN = 230 MHz | 69.1 | 69.3 | |||||||
NSD | Noise spectral density (averaged across Nyquist zone) |
fIN = 10 MHz | 146.3 | 146.4 | dBFS/Hz | ||||
fIN = 70 MHz | –144.8 | 146.2 | 146.3 | ||||||
fIN = 100 MHz | 146.0 | 146.2 | |||||||
fIN = 170 MHz | 145.6 | 145.9 | |||||||
fIN = 230 MHz | 145.1 | 145.3 | |||||||
SINAD | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.2 | 70.4 | dBFS | ||||
fIN = 70 MHz | 67.6 | 70.1 | 70.3 | ||||||
fIN = 100 MHz | 70.0 | 70.1 | |||||||
fIN = 170 MHz | 69.5 | 69.7 | |||||||
fIN = 230 MHz | 68.7 | 69.0 | |||||||
ENOB | Effective number of bits | fIN = 10 MHz | 11 | 11.4 | 11.4 | Bits | |||
fIN = 70 MHz | 11.4 | 11.4 | |||||||
fIN = 100 MHz | 11.3 | 11.3 | |||||||
fIN = 170 MHz | 11.2 | 11.3 | |||||||
fIN = 230 MHz | 11.1 | 11.1 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 96 | 92 | dBc | ||||
fIN = 70 MHz | 79.5 | 95 | 92 | ||||||
fIN = 100 MHz | 91 | 88 | |||||||
fIN = 170 MHz | 85 | 84 | |||||||
fIN = 230 MHz | 81 | 80 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 96 | 95 | dBc | ||||
fIN = 70 MHz | 79.5 | 95 | 94 | ||||||
fIN = 100 MHz | 94 | 92 | |||||||
fIN = 170 MHz | 85 | 84 | |||||||
fIN = 230 MHz | 81 | 80 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 98 | 92 | dBc | ||||
fIN = 70 MHz | 81 | 99 | 92 | ||||||
fIN = 100 MHz | 91 | 88 | |||||||
fIN = 170 MHz | 87 | 85 | |||||||
fIN = 230 MHz | 83 | 82 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 99 | 92 | dBc | ||||
fIN = 70 MHz | 87 | 98 | 92 | ||||||
fIN = 100 MHz | 97 | 92 | |||||||
fIN = 170 MHz | 95 | 92 | |||||||
fIN = 230 MHz | 95 | 92 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 93 | 90 | dBc | ||||
fIN = 70 MHz | 77 | 93 | 89 | ||||||
fIN = 100 MHz | 88 | 85 | |||||||
fIN = 170 MHz | 82 | 81 | |||||||
fIN = 230 MHz | 79 | 78 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
90 | 90 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
89 | 89 | |||||||
DNL | Differential nonlinearity | fIN = 70 MHz | ±0.1 | ±0.1 | LSBs | ||||
INL | Integrated nonlinearity | fIN = 70 MHz | ±0.4 | ±0.4 | LSBs |
PARAMETER | TEST CONDITIONS | ADC32J22 (fS = 50 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
DYNAMIC AC CHARACTERISTICS | |||||||||
SNR | Signal-to-noise ratio | fIN = 10 MHz | 69.3 | 70.2 | 70.3 | dBFS | |||
fIN = 70 MHz | 70.0 | 70.1 | |||||||
fIN = 100 MHz | 69.9 | 70.0 | |||||||
fIN = 170 MHz | 69.4 | 69.7 | |||||||
fIN = 230 MHz | 68.0 | 68.1 | |||||||
NSD | Noise spectral density (averaged across Nyquist zone) |
fIN = 10 MHz | –143.3 | 144.1 | 144.3 | dBFS/Hz | |||
fIN = 70 MHz | 143.9 | 144.1 | |||||||
fIN = 100 MHz | 143.8 | 144.0 | |||||||
fIN = 170 MHz | 143.4 | 143.7 | |||||||
fIN = 230 MHz | 141.9 | 142.1 | |||||||
SINAD | Signal-to-noise and distortion ratio | fIN = 10 MHz | 68.1 | 70.1 | 70.2 | dBFS | |||
fIN = 70 MHz | 69.9 | 70.0 | |||||||
fIN = 100 MHz | 69.8 | 69.9 | |||||||
fIN = 170 MHz | 69.2 | 69.5 | |||||||
fIN = 230 MHz | 67.6 | 67.6 | |||||||
ENOB | Effective number of bits | fIN = 10 MHz | 11 | 11.4 | 11.4 | Bits | |||
fIN = 70 MHz | 11.3 | 11.3 | |||||||
fIN = 100 MHz | 11.3 | 11.3 | |||||||
fIN = 170 MHz | 11.2 | 11.2 | |||||||
fIN = 230 MHz | 10.9 | 10.9 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 80.5 | 95 | 92 | dBc | |||
fIN = 70 MHz | 94 | 90 | |||||||
fIN = 100 MHz | 91 | 89 | |||||||
fIN = 170 MHz | 85 | 85 | |||||||
fIN = 230 MHz | 82 | 82 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 80.5 | 96 | 95 | dBc | |||
fIN = 70 MHz | 98 | 97 | |||||||
fIN = 100 MHz | 92 | 91 | |||||||
fIN = 170 MHz | 85 | 85 | |||||||
fIN = 230 MHz | 82 | 82 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 81 | 95 | 92 | dBc | |||
fIN = 70 MHz | 94 | 90 | |||||||
fIN = 100 MHz | 91 | 89 | |||||||
fIN = 170 MHz | 88 | 88 | |||||||
fIN = 230 MHz | 82 | 82 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 87 | 98 | 91 | dBc | |||
fIN = 70 MHz | 95 | 92 | |||||||
fIN = 100 MHz | 90 | 90 | |||||||
fIN = 170 MHz | 96 | 91 | |||||||
fIN = 230 MHz | 93 | 91 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 78 | 92 | 88 | dBc | |||
fIN = 70 MHz | 91 | 87 | |||||||
fIN = 100 MHz | 88 | 86 | |||||||
fIN = 170 MHz | 83 | 82 | |||||||
fIN = 230 MHz | 78 | 78 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
89 | 89 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
86 | 86 | |||||||
DNL | Differential nonlinearity | fIN = 70 MHz | ±0.1 | ±0.1 | LSBs | ||||
INL | Integrated nonlinearity | fIN = 70 MHz | ±0.4 | ±0.4 | LSBs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)(1) | ||||||
VIH | High-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels | 1.2 | V | ||
VIL | Low-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels | 0.4 | V | ||
IIH | High-level input current | SEN | 0 | µA | ||
RESET, SCLK, SDATA, PDN | 10 | µA | ||||
IIL | Low-level input current | SEN | 10 | µA | ||
RESET, SCLK, SDATA, PDN | 0 | µA | ||||
DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM) | ||||||
VIH | High-level input voltage | 1.3 | V | |||
VIL | Low-level input voltage | 0.5 | V | |||
V(CM_DIG) | Common-mode voltage for SYNC~ and SYSREF | 0.9 | V | |||
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB) | ||||||
VOH | High-level output voltage | DVDD – 0.1 | DVDD | V | ||
VOL | Low-level output voltage | 0.1 | V | |||
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2) | ||||||
VOH | High-level output voltage | AVDD | V | |||
VOL | Low-level output voltage | AVDD – 0.4 | V | |||
VOD | Output differential voltage | 0.4 | V | |||
VOC | Output common-mode voltage | AVDD – 0.2 | V | |||
Transmitter short-circuit current | Transmitter pins shorted to any voltage between –0.25 V and 1.45 V | –100 | 100 | mA | ||
zos | Single-ended output impedance | 50 | Ω | |||
Output capacitance | Output capacitance inside the device, from either output to ground |
2 | pF |
MIN | TYP | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|---|
SAMPLE TIMING CHARACTERISTICS | ||||||||
Aperture delay | 0.85 | 1.25 | 1.65 | ns | ||||
Aperture delay matching between two channels on the same device | ±70 | ps | ||||||
Aperture delay matching between two devices at the same temperature and supply voltage | ±150 | ps | ||||||
Aperture jitter | 200 | fS rms | ||||||
Wake-up time to valid data after coming out of STANDBY mode | 35 | 100 | µs | |||||
Wake-up time to valid data after coming out of global power-down | 85 | 300 | µs | |||||
tSU_SYNC~ | Setup time for SYNC~ referenced to input clock rising edge | 1 | ns | |||||
tH_SYNC~ | Hold time for SYNC~ referenced to input clock rising edge | 100 | ps | |||||
tSU_SYSREF | Setup time for SYSREF referenced to input clock rising edge | 1 | ns | |||||
tH_SYSREF | Hold time for SYSREF referenced to input clock rising edge | 100 | ps | |||||
CML OUTPUT TIMING CHARACTERISTICS | ||||||||
Unit interval | 320 | 1667 | ps | |||||
Serial output data rate | 3.125 | Gbps | ||||||
Total jitter: 3.125 Gbps (20X mode, fS = 156.25 MSPS) | 0.3 | P-PUI | ||||||
tR, tF | Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps |
105 | ps |
MODE | PARAMETER | LATENCY (N Cycles) | TYPICAL DATA DELAY (tD, ns) |
---|---|---|---|
20X | ADC latency | 17 | 0.29 × tS + 3 |
Normal OVR latency | 9 | 0.5 × tS + 2 | |
Fast OVR latency | 7 | 0.5 × tS + 2 | |
From SYNC~ falling edge to CGS phase(3) | 15 | 0.3 × tS + 4 | |
From SYNC~ rising edge to ILA sequence(4) | 17 | 0.3 × tS + 4 | |
40X | ADC latency | 16 | 0.85 × tS + 3.9 |
Normal OVR latency | 9 | 0.5 × tS + 2 | |
Fast OVR latency | 7 | 0.5 × tS + 2 | |
From SYNC~ falling edge to CGS phase(3) | 14 | 0.9 × tS + 4 | |
From SYNC~ rising edge to ILA sequence(4) | 12 | 0.9 × tS + 4 |
fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 92.6 dBc |
fS = 160 MSPS, SNR = 69.8 dBFS, fIN = 70 MHz, SFDR = 86 dBc |
fS = 160 MSPS, SNR = 69.1 dBFS, fIN = 170 MHz, SFDR = 83 dBc |
fS = 160 MSPS, SNR = 68.1 dBFS, fIN = 270 MHz, SFDR = 78.6 dBc |
fS = 160 MSPS, SNR = 62.9 dBFS, fIN = 450 MHz, SFDR = 66 dBc |
fS = 160 MSPS, IMD = 92.3 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 160 MSPS, IMD = 82.5 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
RMS noise = 1.3 LSBs |
fS = 160 MSPS, SNR = 70.5 dBFS, fIN = 10 MHz, SFDR = 92.6 dBc |
fS = 160 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 85 dBc |
fS = 160 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz, SFDR = 83 dBc |
fS = 160 MSPS, SNR = 68.6 dBFS, fIN = 270 MHz, SFDR = 78.9 dBc |
fS = 160 MSPS, SNR = 63 dBFS, fIN = 450 MHz, SFDR = 66.6 dBc |
fS = 160 MSPS, IMD = 99.3 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 160 MSPS, IMD = 98.9 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
fS = 125 MSPS, SNR = 70.2 dBFS, fIN = 10 MHz, SFDR = 99.3 dBc |
fS = 125 MSPS, SNR = 70 dBFS, fIN = 70 MHz, SFDR = 91 dBc | ||
fS = 125 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz, SFDR = 85 dBc |
fS = 125 MSPS, SNR = 68.8 dBFS, fIN = 270 MHz, SFDR = 80.5 dBc |
fS = 125 MSPS, SNR = 63.5 dBFS, fIN = 450 MHz, SFDR = 68.6 dBc |
fS = 125 MSPS, IMD = 94.7 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 125 MSPS, IMD = 96.2 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
RMS noise = 1.4 LSBs |
fS = 125 MSPS, SNR = 70.6 dBFS, fIN = 10 MHz, SFDR = 93.8 dBc |
fS = 125 MSPS, SNR = 70.2 dBFS, fIN = 70 MHz, SFDR = 90 dBc |
fS = 125 MSPS, SNR = 69.9 dBFS, fIN = 70 MHz, SFDR = 84 dBc |
fS = 125 MSPS, SNR = 69.3 dBFS, fIN = 270 MHz, SFDR = 79.9 dBc |
fS = 125 MSPS, SNR = 63.8 dBFS, fIN = 450 MHz, SFDR = 68.8 dBc |
fS = 125 MSPS, IMD = 98.73 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 125 MSPS, IMD = 97 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
fS = 80 MSPS, SNR = 70.1 dBFS, fIN = 10 MHz, SFDR = 95.4 dBc |
fS = 80 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 93 dBc |
fS = 80 MSPS, SNR = 69.3 dBFS, fIN = 170 MHz, SFDR = 86 dBc |
fS = 80 MSPS, SNR = 68.9 dBFS, fIN = 270 MHz, SFDR = 76.9 dBc |
fS = 80 MSPS, SNR = 62.7 dBFS, fIN = 450 MHz, SFDR = 67.6 dBc |
fS = 80 MSPS, IMD = 96 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 80 MSPS, IMD = 92.1 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
RMS noise = 1.4 LSBs |
fS = 80 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 89.7 dBc |
fS = 80 MSPS, SNR = 70.3 dBFS, fIN = 70 MHz, SFDR = 92 dBc |
fS = 80 MSPS, SNR = 69.6 dBFS, fIN = 10 MHz, SFDR = 85 dBc | ||
fS = 80 MSPS, SNR = 69 dBFS, fIN = 270 MHz, SFDR = 76.5 dBc |
fS = 80 MSPS, SNR = 61.8 dBFS, fIN = 450 MHz, SFDR = 67.4 dBc |
fS = 80 MSPS, IMD = 98.5 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 80 MSPS, IMD = 97.5 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
fS = 50 MSPS, SNR = 70.2 dBFS, fIN = 10 MHz, SFDR = 97.6 dBc |
fS = 50 MSPS, SNR = 69.9 dBFS, fIN = 70 MHz, SFDR = 92 dBc |
fS = 50 MSPS, SNR = 68.6 dBFS, fIN = 170 MHz, SFDR = 86 dBc |
fS = 50 MSPS, SNR = 68.4 dBFS, fIN = 270 MHz, SFDR = 75.7 dBc |
fS = 50 MSPS, SNR = 65.3 dBFS, fIN = 450 MHz, SFDR = 67.4 dBc |
fS = 50 MSPS, IMD = 90.2 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 50 MSPS, IMD = 91.2 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
RMS noise = 1.3 LSBs |
fS = 50 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 90.8 dBc |
fS = 50 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 91 dBc |
fS = 50 MSPS, SNR = 69.1 dBFS, fIN = 170 MHz, SFDR = 85 dBc |
fS = 50 MSPS, SNR = 68.6 dBFS, fIN = 270 MHz, SFDR = 75.6 dBc |
fS = 50 MSPS, SNR = 65.2 dBFS, fIN = 450 MHz, SFDR = 67 dBc |
fS = 50 MSPS, IMD = 95.5 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz |
fS = 50 MSPS, IMD = 96.8 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz |
fS = 160 MSPS, fCM = 10 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fCM ) = –98 dBFS, Amplitude (fIN – fCM ) = –91 dBFS |
fS = 160 MSPS, fPSRR = 5 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fPSRR ) = –65 dBFS, Amplitude (fIN – fPSRR ) = –67 dBFS |
The ADC32J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support a JESD204B interface in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 0, 1, 2 with interface data rates up to 3.2 Gbps.
The ADC32J2x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving 50-Ω termination between INP and INM).
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC32J2x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer.
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 152. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, a clock source with very low jitter is recommended. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.
The signal-to-noise ratio of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter noise, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is 74 dB for a 12-bit ADC. Thermal noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2:
The total clock jitter (TJitter) has two components: the internal aperture jitter (200 fs for the device) that is set by the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3:
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input and a faster clock slew rate improves the ADC aperture jitter. The devices have a thermal noise of 73.5 dBFS and internal aperture jitter of 200 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 153.
The devices are equipped with an internal divider on the clock input. The divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for operation with a 160-MHz clock, the divide-by-2 option supports a maximum input clock of 320 MHz, and the divide-by-4 option supports a maximum input clock frequency of 640 MHz.
The power-down functions of the ADC32J2x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality.
FUNCTION | POWER CONSUMPTION (mW) | WAKE-UP TIME (µs) |
---|---|---|
Global power-down | 5 | 85 |
Standby | 118 | 35 |
The ADC32J2x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect of using dither algorithms.
fS = 160 MSPS, SNR = 69.8 dBFS, fIN = 70 MHz, SFDR = 88.1 dBc |
fS = 160 MSPS, SNR = 70.1 dBFS, fIN = 70 MHz, SFDR = 85.4 dBc |
The ADC32J2x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial transmitter, as shown in Figure 156. The data of each ADC are serialized by 20X using an internal PLL and then transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC (subclass 2) signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.
The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and determines if the ADC output data or test patterns are transmitted. The link layer performs the 8b or 10b data encoding and the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled.
The initial lane alignment process is started by the receiving device by asserting the SYNC signal. When a logic high is detected on the SYNC input pins, the ADC32J2x starts transmitting comma (K28.5) characters to establish code group synchronization. When synchronization is complete, the receiving device de-asserts the SYNC signal and the ADC32J2x starts the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32J2x transmits four multiframes, each containing K frames (K is SPI programmable). Each multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration data.
There are three different test patterns available in the transport layer of the JESD204B interface. The ADC32J2x supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled via SPI register writes and are located in address 26h (bits 7:6).
The JESD204B standard defines the following parameters:
L | M | F | S | MINIMUM ADC SAMPLING RATE (MSPS) | MAXIMUM fSERDES (Mbps) | MAXIMUM ADC SAMPLING RATE (Msps) | MAXIMUM fSERDES (GSPS) | MODE |
---|---|---|---|---|---|---|---|---|
2 | 2 | 2 | 1 | 15 | 300 | 160 | 3.2 | 20X (default) |
1 | 2 | 4 | 1 | 10 | 400 | 80 | 3.2 | 40X |
The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration can be changed from 20X (default) to 40X by setting the registers listed in Table 4.
ADDRESS | DATA |
---|---|
2Bh | 01h |
30h | 11h |
The ADC32J2x JESD204B transmitter uses differential CML output drivers. The CML output current is programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential 100-Ω load impedance and place the termination resistors as close to the receiver inputs as possible to avoid unwanted reflections and signal distortion. Because the JESD204B employs 8b, 10b encoding, the output data stream is dc-balanced and ac-coupling can be used to avoid the need to match up common-mode voltages between the transmitter and receivers. Connect the termination resistors to the termination voltage, as shown in Figure 159.
Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B transmitter mask at 3.125 Gbps (156.25 MSPS, 20X mode), respectively.
The input full-scale amplitude can be selected between 1 VPP to 2 VPP (default is 2 VPP) by choosing the appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for SFDR performance. A larger input full-scale increases SNR performance (2 VPP is recommended for maximum SNR) whereas reduced input swing typically results in better SFDR performance. Table 5 lists the available digital gain settings.
DIGITAL GAIN (dB) | MAX INPUT VOLTAGE (VPP) |
---|---|
0 | 2.0 |
0.5 | 1.89 |
1 | 1.78 |
1.5 | 1.68 |
2 | 1.59 |
2.5 | 1.50 |
3 | 1.42 |
3.5 | 1.34 |
4 | 1.26 |
4.5 | 1.19 |
5 | 1.12 |
5.5 | 1.06 |
6 | 1.00 |
The ADC32J2x provides two different overrange indications. The normal OVR (default) is triggered if the final 12-bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction to an overrange event. By default, the normal overrange indication is output on the OVRx pins (where x is A, B, C, or D). The fast OVR indication can be presented on the overrange pins instead by using the SPI register map.
The ADC32J2x can be configured using a serial programming interface, as described in this section.
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 161. If required, the serial interface registers can be cleared during operation either:
The device internal register can be programmed with these steps:
Figure 161 and Table 6 show the timing requirements for the serial register write operation.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDIO setup time | 25 | ns | ||
tDH | SDIO hold time | 25 | ns |
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. Given below is the procedure to read contents of serial registers:
When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 163.
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 164 and Table 7.
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
t1 | Power-on delay from power up to active high RESET pulse | 1 | ms | |||
t2 | Reset pulse duration: active high RESET pulse duration | 10 | 1000 | ns | ||
t3 | Register write delay from RESET disable to SEN active | 100 | ns |
If required, the serial interface registers can be cleared during operation either:
After power-up, the sequence described in Table 8 can be used to set up the ADC32J2x for basic operation.
STEP | DESCRIPTION | REGISTER ADDRESS AND DATA |
---|---|---|
1 | Supply all supply voltages. There is no required power supply sequence for AVDD and DVDD | — |
2 | Pulse hardware reset (low to high to low) on pin 24 | — |
3 | Optional configure LMFS of JESD204B interface to LMFS = 1241 (default is LMFS = 2221) | Address 2Bh, data 01h Address 30h, data 11h |
4 | Pulse SYNCb from low to high to transmit data from k28.5 sync mode | — |
REGISTER ADDRESS (A[13:0], Hex) |
REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
01 | 0 | 0 | DIS DITHER CHA | DIS DITHER CHB | 0 | 0 | ||
03 | 0 | 0 | 0 | 0 | 0 | 0 | CHA GAINEN | 0 |
04 | 0 | 0 | 0 | 0 | 0 | 0 | CHB GAINEN | 0 |
06 | 0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
07 | 0 | 0 | 0 | SPECIAL MODE1 CHA | EN FOVR | 0 | ||
08 | 0 | 0 | 0 | SPECIAL MODE1 CHB | 0 | 0 | ||
09 | 0 | 0 | 0 | 0 | 0 | 0 | ALIGN TEST PATTERN | DATA FORMAT |
0A | 0 | 0 | 0 | 0 | CHA TEST PATTERN | |||
0B | CHB TEST PATTERN | 0 | 0 | 0 | 0 | |||
0C | 0 | 0 | 0 | 0 | CHA DIGITAL GAIN | |||
0D | CHB DIGITAL GAIN | 0 | 0 | 0 | 0 | |||
0E | CUSTOM PATTERN [11:4] | |||||||
0F | CUSTOM PATTERN [3:0] | 0 | 0 | 0 | ||||
13 | LOW SPEED MODE | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
15 | 0 | CHA PDN | CHB PDN | 0 | STANDBY | GLOBAL PDN | 0 | CONFIG PDN PIN |
27 | CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
2A | SERDES TEST PATTERN | IDLE SYNC | TRP LAYER TESTMODE EN |
FLIP ADC DATA |
LANE ALIGN |
FRAME ALIGN | TXMIT LINKDATA DIS |
|
2B | 0 | 0 | 0 | 0 | 0 | 0 | CTRL K | CTRL F |
2F | SCRAMBLE EN | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
30 | OCTETS PER FRAME | |||||||
31 | 0 | 0 | 0 | FRAMES PER MULTIFRAME | ||||
34 | SUBCLASSV | 0 | 0 | 0 | 0 | 0 | ||
3A | SYNC REG | SYNC REQ EN | 0 | 0 | OUTPUT CURRENT SEL | |||
3B | LINK LAYER TESTMODE SEL [2:0] | LINK LAYER RPAT | 0 | PULSE DET MODES | ||||
3C | FORCE LMFC COUNT | LMFC COUNT INIT | RELEASE ILANE SEQ | |||||
422 | 0 | 0 | 0 | 0 | 0 | 0 | SPECIAL MODE2 CHA |
0 |
434 | 0 | 0 | DIS DITH CHA | 0 | DIS DITH CHA | 0 | 0 | 0 |
522 | 0 | 0 | 0 | 0 | 0 | 0 | SPECIAL MODE2 CHB |
0 |
534 | 0 | 0 | DIS DITH CHB | 0 | DIS DITH CHB | 0 | 0 | 0 |
Table 10 lists the location, value, and functions of special mode registers in the device.
MODE | LOCATION | VALUE AND FUNCTION | |
---|---|---|---|
Dither mode | DIS DITH CHA | 01h (bits 5-4), 434h (bits 5, 3) | Creates a noise floor cleaner and improves SFDR; see the Internal Dither Algorithm section. 0000 = Dither disabled 1111 = Dither enabled |
DIS DITH CHB | 01h (bits 3-2), 534h (bits 5, 3) | ||
Special mode 1 | SPECIAL MODE 1 CHA | 07h (bits 4-2) | Use for improved HD3. 000 = Default after reset 010 = Use for frequency < 120 MHz 111 = Use for frequency > 120 MHz |
SPECIAL MODE 1 CHB | 08h (bits 4-2) | ||
Special mode 2 | SPECIAL MODE 2 CHA | 422h (bits 1-0) | Helps improve HD2. 00 = Default after reset 11 = Improves HD2 |
SPECIAL MODE 2 CHB | 522h (bits 1-0) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITHER CHA | DIS DITHER CHB | 0 | 0 | ||
W-0h | W-0h | R/W-0h | R/W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0 |
5-4 | DIS DITHER CHA | R/W | 0h | These bits enable or disables the on-chip dither. Control these bits with bits 5 and 3 of register 434h. 00 = Dither enabled 11 = Dither disabled. Improves SNR by 0.2 dB for input frequencies up to 170 MHz. |
3-2 | DIS DITHER CHB | R/W | 0h | These bits enable or disables the on-chip dither. Control these bits with bits 5 and 3 of register 534h. 00 = Dither enabled 11 = Dither disabled. Improves SNR by 0.2 dB for input frequencies up to 170 MHz. |
1-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | CHA GAINEN | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | CHA GAINEN | R/W | 0h | Digital gain enable bit for channel A. 0 = Digital gain disabled 1 = Digital gain enabled |
0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | CHB GAINEN | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | CHB GAINEN | R/W | 0h | Digital gain enable bit for channel B. 0 = Digital gain disabled 1 = Digital gain enabled |
0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | TEST PATTERN EN | R/W | 0h | This bit enables the test pattern selection for the digital outputs. 0 = Normal operation 1 = Test pattern output enabled |
0 | RESET | R/W | 0h | Software reset applied. This bit resets all internal registers to the default values and self-clears to 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | SPECIAL MODE1 CHA | EN FOVR | 0 | ||
W-0h | W-0h | W-0h | R/W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | 0 | W | 0h | Must write 0 |
4-2 | SPECIAL MODE1 CHA | R/W | 0h | 010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz |
1 | EN FOVR | R/W | 0h | 0 = Normal OVR on OVRx pins 1 = Enable fast OVR on OVRx pins |
0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | SPECIAL MODE1 CHB | 0 | 0 | ||
W-0h | W-0h | W-0h | R/W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | 0 | W | 0h | Must write 0 |
4-2 | SPECIAL MODE1 CHB | R/W | 0h | 010 = For frequencies < 120 MHz 111 = For frequencies > 120 MHz |
1-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | ALIGN TEST PATTERN | DATA FORMAT |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | ALIGN TEST PATTERN | R/W | 0h | This bit aligns test patterns across the outputs of the four channels. 0 = Test patterns of four channels are free running 1 = Test patterns of all 4 channels are aligned |
0 | DATA FORMAT | R/W | 0h | This bit sets the digital output data format. 0 = Twos complement 1 = Offset binary |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | CHA TEST PATTERN | |||
W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0 |
3-0 | CHA TEST PATTERN | R/W | 0h | These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increments by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHB TEST PATTERN | 0 | 0 | 0 | 0 | |||
R/W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CHB TEST PATTERN | R/W | 0h | These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 0110 = Deskew pattern: data are AAAh. 1000 = PRBS pattern: data are a sequence of pseudo random numbers. 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use |
3-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | CHA DIGITAL GAIN | |||
W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0 |
3-0 | CHA DIGITAL GAIN | R/W | 0h | These bits set the digital gain for individual channels. For register settings see Table 21. |
REGISTER VALUE | DIGITAL GAIN (dB) | MAXIMUM INPUT VOLTAGE (VPP) |
---|---|---|
0000 | 0 | 2.0 |
0001 | 0.5 | 1.89 |
0010 | 1 | 1.78 |
0011 | 1.5 | 1.68 |
0100 | 2 | 1.59 |
0101 | 2.5 | 1.50 |
0110 | 3 | 1.42 |
0111 | 3.5 | 1.34 |
1000 | 4 | 1.26 |
1001 | 4.5 | 1.19 |
1010 | 5 | 1.12 |
1011 | 5.5 | 1.06 |
1100 | 6 | 1.00 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHB DIGITAL GAIN | 0 | 0 | 0 | 0 | |||
R/W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CHB DIGITAL GAIN | R/W | 0h | These bits set the digital gain for the individual channels. For register settings see Table 21. |
3-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN[11:4] | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CUSTOM PATTERN[11:4] | R/W | 0h | These bits set the custom pattern[11:4] for all channels. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN[3:0] | 0 | 0 | |||||
R/W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | CUSTOM PATTERN[3:0] | R/W | 0h | These bits set the custom pattern[3:0] for all channels. |
1-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOW SPEED MODE | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | LOW SPEED MODE | R/W | 0h | Use this bit for sampling frequencies < 25 MSPS. 0 = Normal operation 1 = Low-speed mode is enabled |
6-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | CHA PDN | CHB PDN | 0 | STANDBY | GLOBAL PDN |
0 | PDN PIN DISABLE |
W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | W | 0h | Must write 0 |
6 | CHA PDN | R/W | 0h | Power-down channel A. 0 = Normal operation 1 = Power-down channel A if PDN PIN DISABLE register bit is set |
5 | CHB PDN | R/W | 0h | Power-down channel B. 0 = Normal operation 1 = Power-down channel B if PDN PIN DISABLE register bit is set |
4 | 0 | W | 0h | Must write 0 |
3 | STANDBY | R/W | 0h | ADCs of both channels enter standby. 0 = Normal operation 1 = Standby |
2 | GLOBAL PDN | R/W | 0h | Global power-down. 0 = Normal operation 1 = Global power-down |
1 | 0 | W | 0h | Must write 0 |
0 | PDN PIN DISABLE | R/W | 0h | This bit disables the power-down control from the pin. 0 = Normal operation 1 = Power-down pin is disabled, use register settings for power-down operations |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CLK DIV | R/W | 0h | Internal clock divider for the input sample clock. 00 = Clock divider bypassed 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 |
5-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SERDES TEST PATTERN | IDLE SYNC | TRP LAYER TESTMODE EN | FLIP ADC DATA | LANE ALIGN | FRAME ALIGN | TX LINK CONFIG DATA DIS | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SERDES TEST PATTERN | R/W | 0h | 00 = Normal operation 01 = Outputs clock pattern: output is 10101010 pattern 10 = Encoded pattern: output is 1111111100000000 11 = PRBS sequence: output is 215 – 1 |
5 | IDLE SYNC | R/W | 0h | This bit sets the output pattern when SYNC is high. 0 = Sync code is k28.5 (BCBCh) 1 = Sync code is BC50h |
4 | TRP LAYER TESTMODE EN | R/W | 0h | This bit generates the long transport layer test pattern mode according to 5.1.6.3 clause of the JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled |
3 | FLIP ADC DATA | R/W | 0h | 0 = Normal operation 1 = Output data order is reversed: MSB – LSB |
2 | LANE ALIGN | R/W | 0h | This bit inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts lane alignment characters |
1 | FRAME ALIGN | R/W | 0h | This bit inserts a frame alignment character (K28.7) for the receiver to align to the lane boundary per section 5.3.3.4 of the JESD204B specification. 0 = Normal operation 1 = Inserts frame alignment characters |
0 | TX LINK CONFIG DATA DIS | R/W | 0h | This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-asserted. 0 = Normal operation 1 = ILA disabled |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | CTRL K | CTRL F |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | CTRL K | R/W | 0h | Enable bit for number of frames per multiframe. 0 = Default is 9 (20X mode) frames per multiframe 1 = Frames per multiframe can be set in register 31h |
0 | CTRL F | R/W | 0h | Enable bit for number of octets per frame. 0 = 20X mode using one lane per ADC (default is F = 2) 1 = Octets per frame can be specified in register 30h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCRAMBLE EN | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SCRAMBLE EN | R/W | 0h | Scramble enable bit in the JESD204B interface. 0 = Scrambling disabled 1 = Scrambling enabled |
6-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCTETS PER FRAME | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | OCTETS PER FRAME | R/W | 0h | These bits set the number of octets per frame (F). 01 = 20X serialization: two octets per frame 11 = 40X serialization: four octets per frame |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | FRAMES PER MULTI FRAME | ||||
W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | 0 | W | 0h | Must write 0 |
4-0 | FRAMES PER MULTI FRAME | R/W | 0h | These bits set the number of frames per multiframe. After reset, the default settings for frames per multiframe are: 20X mode: K = 8 For each mode, do not set K to a lower value. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUBCLASSV | 0 | 0 | 0 | 0 | 0 | ||
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | SUBCLASSV | R/W | 0h | JESD204B subclass setting. 000 = Subclass 0 backward compatibility with JESD204A 001 = Subclass 1 deterministic latency using SYSREF signal 010 = Subclass 2 deterministic latency using SYNC detection |
4-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC REQ | SYNC REQ EN | 0 | 0 | OUTPUT CURRENT SEL | |||
R/W-0h | R/W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SYNC REQ | R/W | 0h | This bit generates a synchronization request only when the SYNC REQ EN register bit is set. 0 = Normal operation 1 = Generates sync request |
6 | SYNC REQ EN | R/W | 0h | 0 = Sync request is made with the SYNCP~, SYNCM~ pins 1 = Sync request is made with the SYNC REQ register bit |
5-4 | 0 | W | 0h | Must write 0 |
3-0 | OUTPUT CURRENT SEL | R/W | 0h | JESD output buffer current selection. 0000 = 16 mA 0001 = 15 mA 0010 = 14 mA 0011 = 13 mA 0100 = 20 mA 0101 = 19 mA 0110 = 18 mA 0111 = 17 mA 1000 = 8 mA 1001 = 7 mA 1010 = 6 mA 1011 = 5 mA 1100 = 12 mA 1101 = 11 mA 1110 = 10 mA 1111 = 9 mA |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINK LAYER TESTMODE | LINK LAYER RPAT | 0 | PULSE DET MODES | ||||
R/W-0h | R/W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | LINK LAYER TESTMODE | R/W | 0h | These bits generate a pattern according to clause 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high-frequency jitter pattern) 010 = K28.5 (mixed frequency jitter pattern) 011 = Repeat initial lane alignment (generates K28.5 character and repeat lane alignment sequences continuously) 100 = 12 octet RPAT jitter pattern |
4 | LINK LAYER RPAT | R/W | 0h | This bit changes the running disparity in the modified RPAT pattern test mode (only when link layer test mode = 100). 0 = Normal operation 1 = Changes disparity |
3 | 0 | W | 0h | Must write 0 |
2-0 | PULSE DET MODES | R/W | 0h | These bits select different detection modes for SYSREF (subclass 1) and SYNC (subclass2). For register settings see Table 36. |
D2 | D1 | D0 | FUNCTIONALITY |
---|---|---|---|
0 | Don’t care | 0 | Allow all pulses to reset input clock dividers |
1 | Don’t care | 0 | Do not allow reset of analog clock dividers |
Don’t care | 0 to 1 transition | 1 | Allow one pulse immediately after the 0 to1 transition to reset the divider |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FORCE LMFC COUNT | LMFC COUNT INIT | RELEASE ILAN SEQ | |||||
R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FORCE LMFC COUNT | R/W | 0h | 0 = Normal operation 1 = Enables using different starting value for LMFC counter |
6-2 | LMFC COUNT INIT | R/W | 0h | If SYSREF is transmitted to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx receives the LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled. |
1-0 | RELEASE ILAN SEQ | R/W | 0h | These bits delay the lane alignment sequence generation by 0, 1, 2, or 3 multiframes after the code group synchronization. 00 = 0 01 = 1 10 = 2 11 = 3 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | SPECIAL MODE2 CHA | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | SPECIAL MODE2 CHA | R/W | 0h | Always write 1 for improved HD2 performance. |
0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHA | 0 | DIS DITH CHA | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0 |
5 | DIS DITH CHA | R/W | 0h | Set this bit along with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0 |
3 | DIS DITH CHA | R/W | 0h | Set this bit along with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | SPECIAL MODE2 CHB | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | SPECIAL MODE2 CHB | R/W | 0h | Always write 1 for better HD2 performance. |
0 | 0 | W | 0h | Must write 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHB | 0 | DIS DITH CHB | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0 |
5 | DIS DITH CHB | R/W | 0h | Set this bit along with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0 |
3 | DIS DITH CHB | R/W | 0h | Set this bit along with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.5 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0 |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 194 and Figure 195 show the impedance (Zin = Rin || Cin) across the ADC input pins.
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.
A typical application using two back-to-back coupled transformers is illustrated in Figure 196. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the series inductor (39 nH), this combination helps absorb the sampling glitches.
Figure 197 shows the performance obtained by using the circuit shown in Figure 196.
fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 92.6 dBc | ||
See the Design Requirements section for further details.
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 198.
Figure 199 shows the performance obtained by using the circuit shown in Figure 198.
fS = 160 MSPS, SNR = 69.1 dBFS, fIN = 170 MHz, SFDR = 93.5 dBc |
See the Design Requirements section for further details.
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 200.
Figure 201 shows the performance obtained by using the circuit shown in Figure 200.
fS = 160 MSPS, SNR = 62.9 dBFS, fIN = 450 MHz, SFDR = 66 dBc |
The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply requirements during device power-up. AVDD and DVDD can power up in any order.
The ADC32J2x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 202. Some important points to remember when laying out the board are:
Table 42 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
ADC32J22 | Click here | Click here | Click here | Click here | Click here |
ADC32J23 | Click here | Click here | Click here | Click here | Click here |
ADC32J24 | Click here | Click here | Click here | Click here | Click here |
ADC32J25 | Click here | Click here | Click here | Click here | Click here |
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
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