SBAS668A May 2014 – June 2015 ADC32J22 , ADC32J23 , ADC32J24 , ADC32J25
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 194 and Figure 195 show the impedance (Zin = Rin || Cin) across the ADC input pins.
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.
A typical application using two back-to-back coupled transformers is illustrated in Figure 196. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the series inductor (39 nH), this combination helps absorb the sampling glitches.
Figure 197 shows the performance obtained by using the circuit shown in Figure 196.
fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz, SFDR = 92.6 dBc | ||
See the Design Requirements section for further details.
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 198.
Figure 199 shows the performance obtained by using the circuit shown in Figure 198.
fS = 160 MSPS, SNR = 69.1 dBFS, fIN = 170 MHz, SFDR = 93.5 dBc |
See the Design Requirements section for further details.
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 200.
Figure 201 shows the performance obtained by using the circuit shown in Figure 200.
fS = 160 MSPS, SNR = 62.9 dBFS, fIN = 450 MHz, SFDR = 66 dBc |