The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC32J4x | VQFN (48) | 7.00 mm × 7.00 mm |
Changes from * Revision (May 2014) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 4, 5, 8, 9, 12, 17, 20, 25, 28, 29, 32, 39, 46 | I | Analog 1.8-V power supply |
CLKM | 18 | I | Negative differential clock input for the ADC |
CLKP | 19 | I | Positive differential clock input for the ADC |
DAM | 48 | O | Negative serial JESD204B output for channel A |
DAP | 47 | O | Positive serial JESD204B output for channel A |
DBM | 45 | O | Negative serial JESD204B output for channel B |
DBP | 44 | O | Positive serial JESD204B output for channel B |
DVDD | 3,34 | I | Digital 1.8-V power supply |
GND | PowerPAD™ | I | Ground, 0 V |
INAM | 11 | I | Negative differential analog input for channel A |
INAP | 10 | I | Positive differential analog input for channel A |
INBM | 26 | I | Negative differential analog input for channel B |
INBP | 27 | I | Positive differential analog input for channel B |
NC | 2, 6, 7, 30, 31, 35, 37, 38, 40, 41 | — | Do not connect |
OVRA | 1 | O | Overrange indicator for channel A |
OVRB | 36 | O | Overrange indicator for channel B |
PDN | 33 | I | Power-down control. This pin has an internal 150-kΩ pulldown resistor. |
RESET | 21 | I | Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. |
SCLK | 13 | I | Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. |
SDATA | 14 | I | Serial Interface data input. This pin has an internal 150-kΩ pulldown resistor. |
SDOUT | 16 | O | Serial interface data output |
SEN | 15 | I | Serial interface enable. This pin has an internal 150-kΩ pullup resistor to AVDD. |
SYNCM~ | 42 | I | Positive JESD204B SYNC~ input |
SYNCP~ | 43 | I | Negative JESD204B SYNC~ input |
SYSREFM | 23 | I | Negative external SYSREF input |
SYSREFP | 22 | I | Positive external SYSREF input |
VCM | 24 | O | Common-mode voltage output for analog inputs |