SBAS663A May   2014  – June 2015 ADC32J42 , ADC32J43 , ADC32J44 , ADC32J45

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: ADC32J44, ADC32J45
    7. 7.7  Electrical Characteristics: ADC32J42, ADC32J43
    8. 7.8  AC Performance: ADC32J45
    9. 7.9  AC Performance: ADC32J44
    10. 7.10 AC Performance: ADC32J43
    11. 7.11 AC Performance: ADC32J42
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements
    14. 7.14 Typical Characteristics: ADC32J45
    15. 7.15 Typical Characteristics: ADC32J44
    16. 7.16 Typical Characteristics: ADC32J43
    17. 7.17 Typical Characteristics: ADC32J42
    18. 7.18 Typical Characteristics: Common Plots
    19. 7.19 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Maps
      1. 9.6.1 Summary of Special Mode Registers
      2. 9.6.2 Serial Register Descriptions
        1. 9.6.2.1  Register 01h (address = 01h)
        2. 9.6.2.2  Register 03h (address = 03h)
        3. 9.6.2.3  Register 04h (address = 04h)
        4. 9.6.2.4  Register 06h (address = 06h)
        5. 9.6.2.5  Register 07h (address = 07h)
        6. 9.6.2.6  Register 08h (address = 08h)
        7. 9.6.2.7  Register 09h (address = 09h)
        8. 9.6.2.8  Register 0Ah (address = 0Ah)
        9. 9.6.2.9  Register 0Bh (address = 0Bh)
        10. 9.6.2.10 Register 0Ch (address = 0Ch)
        11. 9.6.2.11 Register 0Dh (address = 0Dh)
        12. 9.6.2.12 Register 0Eh (address = 0Eh)
        13. 9.6.2.13 Register 0Fh (address = 0Fh)
        14. 9.6.2.14 Register 13h (address = 13h)
        15. 9.6.2.15 Register 15h (address = 15h)
        16. 9.6.2.16 Register 27h (address = 27h)
        17. 9.6.2.17 Register 2Ah (address = 2Ah)
        18. 9.6.2.18 Register 2Bh (address = 2Bh)
        19. 9.6.2.19 Register 2Fh (address = 2Fh)
        20. 9.6.2.20 Register 30h (address = 30h)
        21. 9.6.2.21 Register 31h (address = 31h)
        22. 9.6.2.22 Register 34h (address = 34h)
        23. 9.6.2.23 Register 3Ah (address = 3Ah)
        24. 9.6.2.24 Register 3Bh (address = 3Bh)
        25. 9.6.2.25 Register 3Ch (address = 3Ch)
        26. 9.6.2.26 Register 422h (address = 422h)
        27. 9.6.2.27 Register 434h (address = 434h)
        28. 9.6.2.28 Register 522h (address = 522h)
        29. 9.6.2.29 Register 534h (address = 534h)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range, AVDD –0.3 2.1 V
Supply voltage range, DVDD –0.3 2.1 V
Voltage applied to
input pins:		 INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 Minimum
(AVDD + 0.3, 2.1)		 V
CLKP, CLKM(2) –0.3 Minimum
(AVDD + 0.3, 2.1)		 V
SYSREFP, SYSREFM, SYNCP~, SYNCM~ –0.3 Minimum
(AVDD + 0.3, 2.1)		 V
SCLK, SEN, SDATA, RESET, PDN –0.3 3.6 V
Temperature Operating free-air, TA –40 85 °C
Operating junction, TJ 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|). This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(2)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage range 1.7 1.8 1.9 V
DVDD Digital supply voltage range 1.7 1.8 1.9 V
ANALOG INPUT
VID Differential input voltage For input frequencies < 450 MHz 2 VPP
For input frequencies < 600 MHz 1 VPP
VIC Input common-mode voltage VCM ± 0.025 V
CLOCK INPUT
Input clock frequency Sampling clock frequency 15 160(1) MSPS
Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 V
LVPECL, ac-coupled 1.6 V
LVDS, ac-coupled 0.7 V
Input clock duty cycle 35% 50% 65%
Input clock common-mode voltage 0.95 V
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF
RLOAD Single-ended load resistance 50 Ω
(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS.
(2) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.

7.4 Thermal Information

THERMAL METRIC(1) ADC32J4x UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 25.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W
RθJB Junction-to-board thermal resistance 3.0 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Differential input full-scale 2.0 VPP
ri Input resistance Differential at dc 6.5 kΩ
ci Input capacitance Differential at dc 5.2 pF
VOC(VCM) VCM common-mode voltage output 0.95 V
VCM output current capability 10 mA
Input common-mode current Per analog input pin 1.5 µA/MSPS
Analog input bandwidth (3 dB) 50-Ω differential source driving a
50-Ω termination across INP, INM		 450 MHz
DC ACCURACY
EO Offset error –20 20 mV
EG(REF) Gain error as a result of internal reference inaccuracy alone –3 3 %FS
EG(CHAN) Gain error of channel alone ±1 %FS
α(EGCHAN) Temperature coefficient of EG(CHAN) –0.017 Δ%FS/Ch
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk(1) fIN = 10 MHz 105 dB
fIN = 100 MHz 105 dB
fIN = 200 MHz 105 dB
fIN = 230 MHz 105 dB
fIN = 300 MHz 105 dB
(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.

7.6 Electrical Characteristics: ADC32J44, ADC32J45

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC32J44 ADC32J45 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 125 160 MSPS
Resolution 14 14 Bits
1.8-V analog supply current 177 292 192 302 mA
1.8-V digital supply current 46 65 56 80 mA
Total power dissipation 401 535 454 560 mW
Global power-down dissipation 5 5 mW
Wake-up time from global power-down 85 85 us
Standby power-down dissipation 112 118 mW
Wake-up time from standby power-down 35 35 µs

7.7 Electrical Characteristics: ADC32J42, ADC32J43

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC32J42 ADC32J43 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 50 80 MSPS
Resolution 14 14 Bits
1.8-V analog supply current 134 267 152 272 mA
1.8-V digital supply current 22 45 31 46 mA
Total power dissipation 281 435 329 450 mW
Global power-down dissipation 5 5 mW
Wake-up time from global power-down 85 85 us
Standby power-down dissipation 99 105 mW
Wake-up time from standby power-down 35 35 µs

7.8 AC Performance: ADC32J45

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J45 (fS = 160 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 72.5 72.8 dBFS
fIN = 70 MHz 70.2 71.7 72.0
fIN = 100 MHz 71.3 71.6
fIN = 170 MHz 70.1 70.7
fIN = 230 MHz 68.9 69.5
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 151.5 151.8 dBFS/Hz
fIN = 70 MHz –149.5 150.7 151.0
fIN = 100 MHz 150.3 150.6
fIN = 170 MHz 149.1 149.7
fIN = 230 MHz 147.9 148.5
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 72.3 72.6 dBFS
fIN = 70 MHz 68.3 71.5 71.8
fIN = 100 MHz 71.0 71.2
fIN = 170 MHz 69.6 70.1
fIN = 230 MHz 68.3 68.4
ENOB Effective number of bits fIN = 10 MHz 11.7 11.8 Bits
fIN = 70 MHz 11.1 11.6 11.6
fIN = 100 MHz 11.5 11.5
fIN = 170 MHz 11.3 11.3
fIN = 230 MHz 11.0 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 90 88 dBc
fIN = 70 MHz 81 85 85
fIN = 100 MHz 85 84
fIN = 170 MHz 84 83
fIN = 230 MHz 81 80
HD2 Second-order harmonic distortion fIN = 10 MHz 90 91 dBc
fIN = 70 MHz 81 91 92
fIN = 100 MHz 88 86
fIN = 170 MHz 84 83
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 91 88 dBc
fIN = 70 MHz 81 85 84
fIN = 100 MHz 85 84
fIN = 170 MHz 91 86
fIN = 230 MHz 86 87
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 98 95 dBc
fIN = 70 MHz 87 99 95
fIN = 100 MHz 97 94
fIN = 170 MHz 92 91
fIN = 230 MHz 91 89
THD Total harmonic distortion fIN = 10 MHz 87 84 dBc
fIN = 70 MHz 78 84 83
fIN = 100 MHz 83 82
fIN = 170 MHz 82 80
fIN = 230 MHz 79 77
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 90 90 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86
DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs

7.9 AC Performance: ADC32J44

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J44 (fS = 125 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 72.6 72.8 dBFS
fIN = 70 MHz 70.8 72.3 72.5
fIN = 100 MHz 72.1 72.3
fIN = 170 MHz 70.1 71.7
fIN = 230 MHz 70.0 70.8
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 150.6 150.8 dBFS/Hz
fIN = 70 MHz –148.8 150.3 150.5
fIN = 100 MHz 150.1 150.3
fIN = 170 MHz 148.1 149.7
fIN = 230 MHz 148.0 148.8
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 72.5 72.7 dBFS
fIN = 70 MHz 68.6 72.2 72.4
fIN = 100 MHz 72.0 72.2
fIN = 170 MHz 70.7 71.4
fIN = 230 MHz 69.5 70.2
ENOB Effective number of bits fIN = 10 MHz 11.8 11.8 Bits
fIN = 70 MHz 11.1 11.7 11.7
fIN = 100 MHz 11.7 11.7
fIN = 170 MHz 11.4 11.6
fIN = 230 MHz 11.2 11.4
SFDR Spurious-free dynamic range fIN = 10 MHz 94 92 dBc
fIN = 70 MHz 81 93 91
fIN = 100 MHz 93 90
fIN = 170 MHz 85 84
fIN = 230 MHz 82 81
HD2 Second-order harmonic distortion fIN = 10 MHz 95 92 dBc
fIN = 70 MHz 81 94 94
fIN = 100 MHz 93 91
fIN = 170 MHz 85 84
fIN = 230 MHz 82 81
HD3 Third-order harmonic distortion fIN = 10 MHz 96 92 dBc
fIN = 70 MHz 82 93 90
fIN = 100 MHz 93 90
fIN = 170 MHz 88 88
fIN = 230 MHz 91 93
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 96 dBc
fIN = 70 MHz 87 99 96
fIN = 100 MHz 98 96
fIN = 170 MHz 98 95
fIN = 230 MHz 96 91
THD Total harmonic distortion fIN = 10 MHz 91 87 dBc
fIN = 70 MHz 78 90 87
fIN = 100 MHz 90 87
fIN = 170 MHz 83 82
fIN = 230 MHz 80 79
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 91 91 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86
DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs

7.10 AC Performance: ADC32J43

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J43 (fS = 80 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 72.3 72.6 dBFS
fIN = 70 MHz 70.8 72.2 72.4
fIN = 100 MHz 72.0 72.2
fIN = 170 MHz 71.4 71.8
fIN = 230 MHz 70.6 71.0
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 148.4 148.7 dBFS/Hz
fIN = 70 MHz –146.8 148.2 148.4
fIN = 100 MHz 148.0 148.2
fIN = 170 MHz 147.4 147.8
fIN = 230 MHz 146.6 147.0
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 72.3 72.5 dBFS
fIN = 70 MHz 68.6 72.2 72.2
fIN = 100 MHz 71.9 72.0
fIN = 170 MHz 71.0 71.4
fIN = 230 MHz 69.9 70.2
ENOB Effective number of bits fIN = 10 MHz 11.7 11.8 Bits
fIN = 70 MHz 11.1 11.7 11.7
fIN = 100 MHz 11.6 11.7
fIN = 170 MHz 11.5 11.6
fIN = 230 MHz 11.3 11.4
SFDR Spurious-free dynamic range fIN= 10 MHz 96 91 dBc
fIN = 70 MHz 82 95 90
fIN = 100 MHz 91 88
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD2 Second-order harmonic distortion fIN = 10 MHz 96 95 dBc
fIN = 70 MHz 81 98 96
fIN = 100 MHz 93 91
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 95 93 dBc
fIN = 70 MHz 83 92 92
fIN = 100 MHz 91 88
fIN = 170 MHz 92 91
fIN = 230 MHz 83 83
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 93 dBc
fIN = 70 MHz 87 99 93
fIN = 100 MHz 97 92
fIN = 170 MHz 97 93
fIN = 230 MHz 95 92
THD Total harmonic distortion fIN = 10 MHz 93 87 dBc
fIN = 70 MHz 78 93 87
fIN = 100 MHz 87 85
fIN = 170 MHz 83 82
fIN = 230 MHz 79 77
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 90 90 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 89 89
DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs

7.11 AC Performance: ADC32J42

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC32J42 (fS = 50 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
DYNAMIC AC CHARACTERISTICS
SNR Signal-to-noise ratio fIN = 10 MHz 71.3 72.2 72.5 dBFS
fIN = 70 MHz 71.8 72.1
fIN = 100 MHz 71.8 72.0
fIN = 170 MHz 71.1 71.5
fIN = 230 MHz 69.1 69.4
NSD Noise spectral density
(averaged across Nyquist zone)		 fIN = 10 MHz 146.1 146.5 dBFS/Hz
fIN = 70 MHz 145.8 146.1
fIN = 100 MHz 145.8 146.0
fIN = 170 MHz 145.1 145.5
fIN = 230 MHz 143.1 143.4
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 69.1 72.1 72.3 dBFS
fIN = 70 MHz 71.8 71.9
fIN = 100 MHz 71.7 71.8
fIN = 170 MHz 70.8 71.1
fIN = 230 MHz 68.4 68.7
ENOB Effective number of bits fIN = 10 MHz 11.2 11.7 11.7 Bits
fIN = 70 MHz 11.6 11.7
fIN = 100 MHz 11.6 11.6
fIN = 170 MHz 11.5 11.5
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 84.5 95 93 dBc
fIN = 70 MHz 95 90
fIN = 100 MHz 91 89
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD2 Second-order harmonic distortion fIN = 10 MHz 84.5 95 94 dBc
fIN = 70 MHz 97 96
fIN = 100 MHz 92 92
fIN = 170 MHz 85 84
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 84.5 102 93 dBc
fIN = 70 MHz 95 90
fIN = 100 MHz 91 89
fIN = 170 MHz 88 88
fIN = 230 MHz 82 83
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 87 98 91 dBc
fIN = 70 MHz 94 92
fIN = 100 MHz 91 91
fIN = 170 MHz 96 92
fIN = 230 MHz 93 91
THD Total harmonic distortion fIN = 10 MHz 79.5 92 90 dBc
fIN = 70 MHz 91 87
fIN = 100 MHz 88 85
fIN = 170 MHz 83 82
fIN = 230 MHz 78 78
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 90 90 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 86 86
DNL Differential nonlinearity fIN = 70 MHz ±0.3 ±0.3 LSBs
INL Integrated nonlinearity fIN = 70 MHz ±1.5 ±1.5 LSBs

7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)(1)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 1.2 V
VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V logic levels 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDATA, PDN 10 µA
IIL Low-level input current SEN 10 µA
RESET, SCLK, SDATA, PDN 0 µA
DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM)
VIH High-level input voltage 1.3 V
VIL Low-level input voltage 0.5 V
V(CM_DIG) Common-mode voltage for SYNC~ and SYSREF 0.95 V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOH High-level output voltage AVDD V
VOL Low-level output voltage AVDD – 0.4 V
VOD Output differential voltage 0.4 V
VOC Output common-mode voltage AVDD – 0.2 V
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Output capacitance Output capacitance inside the device,
from either output to ground		 2 pF
(1) The RESET, SCLK, SDATA, and PDN pins have a 150-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 150-kΩ (typical) pullup resistor to AVDD.
(2) 50-Ω, single-ended external termination to 1.8 V.

7.13 Timing Requirements

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. See Figure 143.
MIN TYP MAX UNITS
SAMPLE TIMING REQUIREMENTS
Aperture delay 0.85 1.25 1.65 ns
Aperture delay matching Between four channels on the same device ±70 ps
Between two devices at the same temperature and supply voltage ±150 ps
Aperture jitter 200 fS rms
Wake-up time Time to valid data after coming out of STANDBY mode 35 100 µs
Time to valid data after coming out of global power-down 85 300 µs
tSU_SYNC~ Setup time for SYNC~ referenced to input clock rising edge 1 ns
tH_SYNC~ Hold time for SYNC~ referenced to input clock rising edge 100 ps
tSU_SYSREF Setup time for SYSREF referenced to input clock rising edge 1 ns
tH_SYSREF Hold time for SYSREF referenced to input clock rising edge 100 ps
CML OUTPUT TIMING REQUIREMENTS
Unit interval 312.5 1667 ps
Serial output data rate 3.2 Gbps
Total jitter: 3.125 Gbps (20X mode, fS = 156.25 MSPS) 0.3 P-PUI
tR, tF Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps 105 ps

Table 1. Latency in Different Modes(1)(2)

MODE PARAMETER LATENCY (N Cycles) TYPICAL DATA DELAY (tD, ns)
20X ADC latency 17 0.29 × tS + 3
Normal OVR latency 9 0.5 × tS + 2
Fast OVR latency 7 0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3) 15 0.3 × tS + 4
From SYNC~ rising edge to ILA sequence(4) 17 0.3 × tS + 4
40X ADC latency 16 0.85 × tS + 3.9
Normal OVR latency 9 0.5 × tS + 2
Fast OVR latency 7 0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3) 14 0.9 × tS + 4
From SYNC~ rising edge to ILA sequence(4) 12 0.9 × tS + 4
(1) Overall latency = latency + tD.
(2) tS is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10X mode and 15 clock cycles in 20X mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10X mode and 11 clock cycles in 20X mode.

7.14 Typical Characteristics: ADC32J45

Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D101_SBAS663.gif
fS = 160 MSPS, SNR = 72.4 dBFS, fIN = 10 MHz,
SFDR = 92.3 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D103_SBAS663.gif
fS = 160 MSPS, SNR = 71.7 dBFS, fIN = 70 MHz,
SFDR = 86 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D105_SBAS663.gif
fS = 160 MSPS, SNR = 70.6 dBFS, fIN = 170 MHz,
SFDR = 85 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D107_SBAS663.gif
fS = 160 MSPS, SNR = 69.3 dBFS, fIN = 270 MHz,
SFDR = 78.9 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D109_SBAS663.gif
fS = 160 MSPS, SNR = 63.2 dBFS, fIN = 450 MHz,
SFDR = 65.7 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D111_SBAS663.gif
fS = 160 MSPS, IMD = 92 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D113_SBAS663.gif
fS = 160 MSPS, IMD = 87 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D115_SBAS663.gif
fS = 160 MSPS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D117_SBAS663.gif
Figure 17. Signal-to-Noise Ratio vs Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D119_SBAS663.gif
Figure 19. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D121_SBAS663.gif
Figure 21. Performance vs Input Amplitude (30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D123_SBAS663.gif
Figure 23. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D125_SBAS663.gif
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D127_SBAS663.gif
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D129_SBAS663.gif
Figure 29. Performance vs Clock Amplitude (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D131_SBAS663.gif
Figure 31. Performance vs Clock Duty Cycle (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D133_SBAS663.gif
RMS noise = 1.3 LSBs
Figure 33. Idle Channel Histogram
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D102_SBAS663.gif
fS = 160 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz,
SFDR = 92.7 dBc
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D104_SBAS663.gif
fS = 160 MSPS, SNR = 72.1 dBFS, fIN = 70 MHz,
SFDR = 85 dBc
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D106_SBAS663.gif
fS = 160 MSPS, SNR = 71.4 dBFS, fIN = 170 MHz,
SFDR = 84 dBc
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D108_SBAS663.gif
fS = 160 MSPS, SNR = 69.9 dBFS, fIN = 270 MHz,
SFDR = 79.3 dBc
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D110_SBAS663.gif
fS = 160 MSPS, SNR = 63.8 dBFS, fIN = 450 MHz,
SFDR = 67 dBc
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D112_SBAS663.gif
fS = 160 MSPS, IMD = 99 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D114_SBAS663.gif
fS = 160 MSPS, IMD = 100 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D116_SBAS663.gif
fS = 160 MSPS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 16. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D118_SBAS663.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D120_SBAS663.gif
Figure 20. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D122_SBAS663.gif
Figure 22. Performance vs Input Amplitude (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D124_SBAS663.gif
Figure 24. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D126_SBAS663.gif
Figure 26. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D128_SBAS663.gif
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D130_SBAS663.gif
Figure 30. Performance vs Clock Amplitude (150 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D132_SBAS663.gif
Figure 32. Performance vs Clock Duty Cycle (150 MHz)

7.15 Typical Characteristics: ADC32J44

Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D301_SBAS663.gif
fS = 125 MSPS, SNR = 72.4 dBFS, fIN = 10 MHz,
SFDR = 98.3 dBc
Figure 34. FFT for 10-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D303_SBAS663.gif
fS = 125 MSPS, SNR = 71.9 dBFS, fIN = 70 MHz,
SFDR = 91 dBc
Figure 36. FFT for 70-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D305_SBAS663.gif
fS = 125 MSPS, SNR = 71 dBFS, fIN = 170 MHz,
SFDR = 86 dBc
Figure 38. FFT for 170-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D307_SBAS663.gif
fS = 125 MSPS, SNR = 70.4 dBFS, fIN = 270 MHz,
SFDR = 80.1 dBc
Figure 40. FFT for 270-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D309_SBAS663.gif
fS = 125 MSPS, SNR = 64.2 dBFS, fIN = 450 MHz,
SFDR = 68.7 dBc
Figure 42. FFT for 450-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D311_SBAS663.gif
fS = 125 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 44. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D313_SBAS663.gif
fS = 125 MSPS, IMD = 88 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 46. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D315_SBAS663.gif
Figure 48. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D317_SBAS663.gif
Figure 50. Signal-to-Noise Ratio vs Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D319_SBAS663.gif
Figure 52. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D321_SBAS663.gif
Figure 54. Performance vs Input Amplitude (30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D323_SBAS663.gif
Figure 56. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D325_SBAS663.gif
Figure 58. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D327_SBAS663.gif
Figure 60. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D329_SBAS663.gif
Figure 62. Performance vs Clock Amplitude (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D331_SBAS663.gif
Figure 64. Performance vs Clock Duty Cycle (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D333_SBAS663.gif
RMS noise = 1.4 LSBs
Figure 66. Idle Channel Histogram
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D302_SBAS663.gif
fS = 125 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz,
SFDR = 94.7 dBc
Figure 35. FFT for 10-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D304_SBAS663.gif
fS = 125 MSPS, SNR = 72.3 dBFS, fIN = 70 MHz,
SFDR = 90 dBc
Figure 37. FFT for 70-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D306_SBAS663.gif
fS = 125 MSPS, SNR = 71.9 dBFS, fIN = 70 MHz,
SFDR = 85 dBc
Figure 39. FFT for 170-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D308_SBAS663.gif
fS = 125 MSPS, SNR = 70.5 dBFS, fIN = 270 MHz,
SFDR = 79.4 dBc
Figure 41. FFT for 270-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D310_SBAS663.gif
fS = 125 MSPS, SNR = 64.6 dBFS, fIN = 450 MHz,
SFDR = 68.9 dBc
Figure 43. FFT for 450-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D312_SBAS663.gif
fS = 125 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D314_SBAS663.gif
fS = 125 MSPS, IMD = 99 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 47. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D316_SBAS663.gif
Figure 49. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D318_SBAS663.gif
Figure 51. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D320_SBAS663.gif
Figure 53. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D322_SBAS663.gif
Figure 55. Performance vs Input Amplitude (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D324_SBAS663.gif
Figure 57. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D326_SBAS663.gif
Figure 59. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D328_SBAS663.gif
Figure 61. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D330_SBAS663.gif
Figure 63. Performance vs Clock Amplitude (150 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D332_SBAS663.gif
Figure 65. Performance vs Clock Duty Cycle (150 MHz)

7.16 Typical Characteristics: ADC32J43

Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D501_SBAS663.gif
fS = 80 MSPS, SNR = 72.2 dBFS, fIN = 10 MHz, SFDR = 93.1 dBc
Figure 67. FFT for 10-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D503_SBAS663.gif
fS = 80 MSPS, SNR = 72.1 dBFS, fIN = 70 MHz, SFDR = 92 dBc
Figure 69. FFT for 70-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D505_SBAS663.gif
fS = 80 MSPS, SNR = 71 dBFS, fIN = 170 MHz, SFDR = 86 dBc
Figure 71. FFT for 170-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D507_SBAS663.gif
fS = 80 MSPS, SNR = 70.2 dBFS, fIN = 270 MHz,
SFDR = 76.9 dBc
Figure 73. FFT for 270-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D509_SBAS663.gif
fS = 80 MSPS, SNR = 64.5 dBFS, fIN = 450 MHz,
SFDR = 67.6 dBc
Figure 75. FFT for 450-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D511_SBAS663.gif
fS = 80 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 77. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D513_SBAS663.gif
fS = 80 MSPS, IMD = 88 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 79. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D515_SBAS663.gif
Figure 81. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D517_SBAS663.gif
Figure 83. Signal-to-Noise Ratio vs Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D519_SBAS663.gif
Figure 85. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D521_SBAS663.gif
Figure 87. Performance vs Input Amplitude (30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D523_SBAS663.gif
Figure 89. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D525_SBAS663.gif
Figure 91. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D527_SBAS663.gif
Figure 93. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D529_SBAS663.gif
Figure 95. Performance vs Clock Amplitude (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D531_SBAS663.gif
Figure 97. Performance vs Clock Duty Cycle (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D533_SBAS663.gif
RMS noise = 1.4 LSBs
Figure 99. Idle Channel Histogram
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D502_SBAS663.gif
fS = 80 MSPS, SNR = 72.6 dBFS, fIN = 10 MHz, SFDR = 91.4 dBc
Figure 68. FFT for 10-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D504_SBAS663.gif
fS = 80 MSPS, SNR = 72.5 dBFS, fIN = 70 MHz, SFDR = 91 dBc
Figure 70. FFT for 70-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D506_SBAS663.gif
fS = 80 MSPS, SNR = 69.7 dBFS, fIN = 10 MHz, SFDR = 85 dBc
Figure 72. FFT for 170-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D508_SBAS663.gif
fS = 80 MSPS, SNR = 70.5 dBFS, fIN = 270 MHz,
SFDR = 76.7 dBc
Figure 74. FFT for 270-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D510_SBAS663.gif
fS = 80 MSPS, SNR = 63.8 dBFS, fIN = 450 MHz,
SFDR = 67.4 dBc
Figure 76. FFT for 450-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D512_SBAS663.gif
fS = 80 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 78. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D514_SBAS663.gif
fS = 80 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 80. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D516_SBAS663.gif
Figure 82. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D518_SBAS663.gif
Figure 84. Spurious-Free Dynamic Range vs Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D520_SBAS663.gif
Figure 86. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D522_SBAS663.gif
Figure 88. Performance vs Input Amplitude (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D524_SBAS663.gif
Figure 90. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D526_SBAS663.gif
Figure 92. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D528_SBAS663.gif
Figure 94. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D530_SBAS663.gif
Figure 96. Performance vs Clock Amplitude (150 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D532_SBAS663.gif
Figure 98. Performance vs Clock Duty Cycle (150 MHz)

7.17 Typical Characteristics: ADC32J42

Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D701_SBAS663.gif
fS = 50 MSPS, SNR = 72.1 dBFS, fIN = 10 MHz, SFDR = 96.2 dBc
Figure 100. FFT for 10-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D703_SBAS663.gif
fS = 50 MSPS, SNR = 71.7 dBFS, fIN = 70 MHz, SFDR = 93.2 dBc
Figure 102. FFT for 70-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D705_SBAS663.gif
fS = 50 MSPS, SNR = 70.4 dBFS, fIN = 170 MHz,
SFDR = 86 dBc
Figure 104. FFT for 170-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D707_SBAS663.gif
fS = 50 MSPS, SNR = 69.5 dBFS, fIN = 270 MHz,
SFDR = 75.7 dBc
Figure 106. FFT for 270-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D709_SBAS663.gif
fS = 50 MSPS, SNR = 65.9 dBFS, fIN = 450 MHz,
SFDR = 67.4 dBc
Figure 108. FFT for 450-MHz Input Signal (Dither On)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D711_SBAS663.gif
fS = 50 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 110. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D713_SBAS663.gif
fS = 50 MSPS, IMD = 86 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 112. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D715_SBAS663.gif
Figure 114. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D717_SBAS663.gif
Figure 116. Signal-to-Noise Ratio vs Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D719_SBAS663.gif
Figure 118. Signal-to-Noise Ratio vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D721_SBAS663.gif
Figure 120. Performance vs Input Amplitude (30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D723_SBAS663.gif
Figure 122. Performance vs Input Common-Mode Voltage (30 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D725_SBAS663.gif
Figure 124. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D727_SBAS663.gif
Figure 126. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D729_SBAS663.gif
Figure 128. Performance vs Clock Amplitude (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D731_SBAS663.gif
Figure 130. Performance vs Clock Duty Cycle (40 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D733_SBAS663.gif
RMS noise = 1.3 LSBs
Figure 132. Idle Channel Histogram
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D702_SBAS663.gif
fS = 50 MSPS, SNR = 72.6 dBFS, fIN = 10 MHz, SFDR = 92.1 dBc
Figure 101. FFT for 10-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D704_SBAS663.gif
fS = 50 MSPS, SNR = 72 dBFS, fIN = 70 MHz, SFDR = 92 dBc
Figure 103. FFT for 70-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D706_SBAS663.gif
fS = 50 MSPS, SNR = 70.9 dBFS, fIN = 170 MHz,
SFDR = 85 dBc
Figure 105. FFT for 170-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D708_SBAS663.gif
fS = 50 MSPS, SNR = 69.5 dBFS, fIN = 270 MHz,
SFDR = 75.7 dBc
Figure 107. FFT for 270-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D710_SBAS663.gif
fS = 50 MSPS, SNR = 66.4 dBFS, fIN = 450 MHz, SFDR = 67 dBc
Figure 109. FFT for 450-MHz Input Signal (Dither Off)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D712_SBAS663.gif
fS = 50 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz
Figure 111. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D714_SBAS663.gif
fS = 50 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 113. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D716_SBAS663.gif
Figure 115. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D718_SBAS663.gif
Figure 117. Spurious-Free Dynamic Range vs
Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D720_SBAS663.gif
Figure 119. Spurious-Free Dynamic Range vs
Digital Gain and Input Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D722_SBAS663.gif
Figure 121. Performance vs Input Amplitude (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D724_SBAS663.gif
Figure 123. Performance vs Input Common-Mode Voltage (170 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D726_SBAS663.gif
Figure 125. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D728_SBAS663.gif
Figure 127. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D730_SBAS663.gif
Figure 129. Performance vs Clock Amplitude (150 MHz)
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D732_SBAS663.gif
Figure 131. Performance vs Clock Duty Cycle (150 MHz)

7.18 Typical Characteristics: Common Plots

Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J42 ADC32J43 ADC32J44 ADC32J45 C040_BAS664.png
fS = 160 MSPS, fCM = 10 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fCM ) = –98 dBFS, Amplitude (fIN – fCM ) = –91 dBFS
Figure 133. CMRR FFT
ADC32J42 ADC32J43 ADC32J44 ADC32J45 C042_BAS664.png
fS = 160 MSPS, fPSRR = 5 MHz, 50 mVPP, fIN = 30 MHz, Amplitude (fIN + fPSRR ) = –65 dBFS, Amplitude (fIN – fPSRR ) = –67 dBFS
Figure 135. PSRR FFT for AVDD Supply
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D005_SBAS663.gif
Figure 137. Power vs Sampling Frequency 20X Mode
ADC32J42 ADC32J43 ADC32J44 ADC32J45 C041_BAS664.png
Figure 134. CMRR vs Test Signal Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 C043_BAS664.png
Figure 136. PSRR vs Test Signal Frequency
ADC32J42 ADC32J43 ADC32J44 ADC32J45 D006_SBAS663.gif
Figure 138. Power vs Sampling Frequency 40X Mode

7.19 Typical Characteristics: Contour Plots

Typical values are at TA= 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
ADC32J42 ADC32J43 ADC32J44 ADC32J45 SFDR_0dB_SBAS663.png
Figure 139. Spurious-Free Dynamic Range (SFDR) for
0-dB Gain
ADC32J42 ADC32J43 ADC32J44 ADC32J45 SNR_0dB_SBAS663.png
Figure 141. Signal-to-Noise Ratio (SNR) for
0-dB Gain
ADC32J42 ADC32J43 ADC32J44 ADC32J45 SFDR_6dB_SBAS663.png
Figure 140. Spurious-Free Dynamic Range (SFDR) for
6-dB Gain
ADC32J42 ADC32J43 ADC32J44 ADC32J45 SNR_6dB_SBAS663.png
Figure 142. Signal-to-Noise Ratio (SNR) for
6-dB Gain