SBAS500B june   2022  – august 2023 ADC32RF54 , ADC32RF55

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
    9. 6.9  Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
    10. 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics - ADC32RF54
    13. 6.13 Typical Characteristics - ADC32RF55
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping Using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDIO pins
          3. 7.3.5.7.3 Fast Frequency Hopping Using the Fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
        7. 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration Using the SPI Interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20221215-CA0I-GXRK-KGFK-LSWMFQ6LHDJQ-low.svg Figure 5-1 RTD Package, 64 Pin VQFNP
(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
ANALOG INPUTS
INA1P 14 I Differential analog input for channel A. 100 Ω (default) or 50 Ω differential internal termination.
INA1M 15
INA2P 18 I Differential analog input for alternate channel A input. This input is used for additional ADC averaging for channel A. 100 Ω (default) or 50 Ω differential internal termination. Should be connected to GND if unused.
INA2M 19
INB1P 35 I Differential analog input for channel B. 100 Ω (default) or 50 Ω differential internal termination.
INB1M 34
INB2P 31 I Differential analog input for alternate channel B input. This input is used for additional ADC averaging for channel B. 100 Ω (default) or 50 Ω differential internal termination. Should be connected to GND if unused.
INB2M 30
VCM 26 O Common-mode voltage output for the analog inputs.
CLOCK, SYNCHRONIZATION
CLKP 23 I Differential sampling clock input. 100 Ω differential internal termination.
CLKM 24
SYSREFP 27 I Differential external synchronization input.
SYSREFM 28
CONTROL
RESET 11 I Hardware reset. Active low. This pin has an internal 21 kΩ pullup resistor to AVDD18.
SEN 57 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18.
SCLK 55 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO 56 I/O Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
GPIO1 39 I GPIO control pin. This pin is configured through SPI interface for power down or NCO control function.
GPIO2 38 I GPIO control pin. This pin is configured through SPI interface for power down or NCO control function.
SPISEL 10 I Determines SPI control: either normal SPI for register writes or fast access to NCO selection only for fast frequency hopping.
DIGITAL DATA INTERFACE
DOUT0P 4 O JESD204B high-speed serial data output interface pins for channel A.
DOUT0M 5
DOUT1P 1
DOUT1M 2
DOUT2P 63
DOUT2M 64
DOUT3P 60
DOUT3M 61
DOUT4P 45 O JESD204B high-speed serial data output interface pins for channel B.
DOUT4M 44
DOUT5P 48
DOUT5M 47
DOUT6P 50
DOUT6M 49
DOUT7P 53
DOUT7M 52
POWER SUPPLY
AVDD18 17,20,29,32, 58 I Analog 1.8-V power supply
AVDD12 13,16,21,33, 36 I Analog 1.2-V power supply
CLKVDD 25 I Clock 1.2-V power supply. Very sensitive to power supply noise. Directly impacts close in aperture phase noise.
DVDD 3,7,9,40,42, 46,54,59 I Digital 1.2-V power supply
AGND 12,37 I Analog ground, shorted to thermal pad.
CLKGND 22 I Clock ground.
DGND 6,8,41,43,51,62 I Digital ground.
(1) I = Input, O = Output, I/O = Input or Output.