SBAS500B june   2022  – august 2023 ADC32RF54 , ADC32RF55

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
    9. 6.9  Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
    10. 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics - ADC32RF54
    13. 6.13 Typical Characteristics - ADC32RF55
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping Using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDIO pins
          3. 7.3.5.7.3 Fast Frequency Hopping Using the Fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
        7. 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration Using the SPI Interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 2.6 GSPS, Bypass mode, No digital averaging, 50% clock duty cycle, AVDD18 = 1.8V, AVDD12, AVDDCLK, DVDD = 1.2V and –1-dBFS differential input, Dither disabled, unless otherwise noted
AIN = -1 dBFS
PARAMETER TEST CONDITIONS MIN(1) TYP MAX UNIT
NSD Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS
no averaging		 –155.5 dBFS/Hz
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 –158.1
fIN = 900 MHz, AIN = -20 dBFS
4x averaging		 –160.9
NF Noise Figure fIN = 900 MHz, AIN = -20 dBFS
no averaging		 20.4 dB
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 19.5
fIN = 900 MHz, AIN = -20 dBFS
4x averaging		 19.7
SNR Signal-to-noise ratio
no (1x) averaging		 fIN = 100 MHz 61.9 dBFS
fIN = 500 MHz 61.9
fIN = 900 MHz 59.3 61.7
fIN = 900 MHz, Ain = -20 dBFS 62.0 64.4
fIN = 1.8 GHz 60.6
fIN = 2.4 GHz 60.0
Signal-to-noise ratio
2x averaging		 fIN = 100 MHz 62.8
fIN = 500 MHz 63.2
fIN = 900 MHz 62.8
fIN = 900 MHz, Ain = -20 dBFS 67.1
fIN = 1.8 GHz 62.5
fIN = 2.4 GHz 61.8
Signal-to-noise ratio
4x averaging		 fIN = 100 MHz 65.5
fIN = 500 MHz 65.9
fIN = 900 MHz 65.6
fIN = 900 MHz, Ain = -20 dBFS 69.8
fIN = 1.8 GHz 65.4
fIN = 2.4 GHz 64.9
SINAD Signal to noise and distortion ratio fIN = 100 MHz 61.4 dBFS
fIN = 500 MHz 60.2
fIN = 900 MHz 59.4
fIN = 1.8 GHz 57.6
fIN = 2.4 GHz 55.3
ENOB Effective number of bits fIN = 100 MHz 9.9 Bits
fIN = 500 MHz 9.7
fIN = 900 MHz 9.6
fIN = 1.8 GHz 9.3
fIN = 2.4 GHz 8.9
THD Total Harmonic Distortion (First five harmonics) fIN = 100 MHz 67 dBc
fIN = 500 MHz 63
fIN = 900 MHz 64
fIN = 1.8 GHz 60
fIN = 2.4 GHz 57
HD2 Second Harmonic Distortion fIN = 100 MHz 72 dBc
fIN = 500 MHz 73
fIN = 900 MHz 62 71
fIN = 1.8 GHz 62
fIN = 2.4 GHz 59
HD3 Third Harmonic Distortion fIN = 100 MHz 75 dBc
fIN = 500 MHz 65
fIN = 900 MHz 60 67
fIN = 1.8 GHz 66
fIN = 2.4 GHz 64
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 100 MHz 76 dBFS
fIN = 500 MHz 74
fIN = 900 MHz 77
fIN = 1.8 GHz 77
fIN = 2.4 GHz 74
IMD3 Two tone inter-modulation distortion f1 = 700 MHz, f2 = 800 MHz, AIN = -7 dBFS/tone 71 dBc
(1) The minimum SNR values are specified by ATE, the HD2,3 by bench characterization