SBAS500B june   2022  – august 2023 ADC32RF54 , ADC32RF55

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - ADC32RF54 AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - ADC32RF54 AC Specifications (Dither ENABLED)
    9. 6.9  Electrical Characteristics - ADC32RF55 AC Specifications (Dither DISABLED)
    10. 6.10 Electrical Characteristics - ADC32RF55 AC Specifications (Dither ENABLED)
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics - ADC32RF54
    13. 6.13 Typical Characteristics - ADC32RF55
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Dynamic Switching
          1. 7.3.5.4.1 2 Lane Mode
          2. 7.3.5.4.2 1 Lane Mode
        5. 7.3.5.5 Numerically Controlled Oscillator (NCO)
        6. 7.3.5.6 NCO Frequency Programming
        7. 7.3.5.7 Fast Frequency Hopping
          1. 7.3.5.7.1 Fast frequency hopping Using the GPIO1/2 pins
          2. 7.3.5.7.2 Fast frequency hopping using GPIO1/2, SEN and SDIO pins
          3. 7.3.5.7.3 Fast Frequency Hopping Using the Fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
        3. 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
        4. 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
        5. 7.3.6.5 JESD204B Frame Assembly with Real Decimation - Single Band
        6. 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Dual Band
        7. 7.3.6.7 JESD204B Frame Assembly with Complex Decimation - Quad Band
      7. 7.3.7 SERDES Output MUX
      8. 7.3.8 Test Pattern
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Link Layer
        3. 7.3.8.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration Using the SPI Interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Sampling Clock
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 STEP 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.6 STEP 6: Analog Trim Settings

The following registers need to be set for best analog performance. The register write order is all writes in first 2 columns before moving to the next set of address/data in middle columns, and so on.

Table 8-9 Analog Trim Setting Registers
ADDR DATA COMMENT ADDR DATA COMMENT ADDR DATA COMMENT
0x05 0x40 0x3B 0x0C Only for FS < 2.9 GSPS 0x56 0x0F
0xE8 0xF0 0xA8 1x AVG: 0x18
2x/4x AVG:
FS<1.1 GSPS: 0x00
FS=1.1-1.8 GSPS: 0x08
FS=1.85-2.6 GSPS: 0x60
FS=2.6-3.0 GSPS: 0x70		 0x6E 0x08
0xE9 0x01 0x102 0x02
0x4B 0x1F 0x103 0xD9
0x5B 0x01 0xA7 0x00
0xEA 0x00 0xA6 0x08
0xEB 0x03 0xCD 0x00 0x05 0x20
0x95 0x00 0xCE 0x00 0xC9 0x09
0xFC 0x28 0x100 See Table 8-10 for sample rate dependent trim registers 0x102 0xFE
0xE0 0x8E 0x101 0x103 0x03
0xE1 0x03 0x104 0x104 0xD4
0x4C 0x40 0x105 0x105 0x03
0x4E 0x01 0x107 0x10 0x106 0xFE
0x4E 0x00 0x05 0x20 0x107 0x03
0xA1 0x01 0x30 0xE8 0x108 0xBC
0xF8 0x00 0x31 0xFF 0x109 0x1A
0x31 0x20 0x30 0x08 0x101 0x01
0xFD 0x1C 0x31 0x80 0x159 0x63
0xAA 0x02 0x32 0x03 0x05 0x40
0x4D 0x80 0x05 0x02 0x31 0x00
0xB3 0x30 0x243 0x02 0x4D 0x00
0x64 0x10 0x05 0x20 0x62 0x10
0x62 0x12 0x36 0x04 0x56 0x0E
0xFE 0x80 0x1F8 0x01 0x56 0x0C
0xFC 0x28 0x1FC 0x0A 0x56 0x08
0xFF 0x14 0x1F0 0x20 0x56 0x00
0x106 0x00 0x1F1 0x0C 0x6E 0x00
0x107 0x00 0x05 0x40 0xF8 0x06
0x3D 0x06 Only for FS> 2.9 GSPS 0x39 0x40 0x102 0x42 Only for FS> 2.9 GSPS
0x104 0x60 0x56 0x01
0xB0 0x00 0x56 0x03
0xB1 0x03 0x56 0x07
Table 8-10 Sample rate dependent trim registers
FS (GSPS) 0x100 0x101 0x104 0x105
0.6-0.7 0x48 0x00 0x01 0x01
0.7-0.9 0xC8 0x01 0x81 0x00
0.9-1.1 0x48 0x01 0x81 0x00
1.1-1.3 0xC8 0x00 0x81 0x00
1.3-1.5 0x48 0x00 0x81 0x00
1.5-1.7 0xC8 0x01 0x01 0x00
1.7-1.9 0x48 0x01 0x01 0x00
1.9-2.1 0xC8 0x00 0x01 0x00
2.1-2.3 0x48 0x00 0x01 0x00
2.3-2.5 0xC8 0x01 0x81 0x03
2.5-2.7 0x48 0x01 0x81 0x03
2.7-2.9 0xC8 0x00 0x81 0x03
2.9-3.0 0x48 0x00 0xE1 0x03