SBAS774B May 2016 – December 2021 ADC32RF80 , ADC32RF83
PRODUCTION DATA
The ADC32RF8x is a dual, 14-bit, 2949.12-MSPS, telecom receiver and feedback device family containing analog-to-digital converters (ADCs) followed by multi-band digital down-converters (DDCs), and a back-end JESD204B digital interface.
The ADCs are preceded by input buffers and on-chip termination to provide a uniform input impedance over a large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection against overvoltage conditions. Each ADC channel is internally interleaved four times and equipped with background, analog and digital, and interleaving correction.
The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent,
16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be controlled through the SPI or GPIO pins. The ADC32RF8x also provides three different power detectors on-chip with alarm outputs in order to support external automatic gain control (AGC) loops.
The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized, and output on one to four lanes per channel, depending on the ADC sampling rate and decimation. The CLKIN, SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link. All features of the ADC32RF8x are configurable through the SPI.