SBAS958A December 2019 – June 2020 ADC3421-Q1
PRODUCTION DATA.
The device internal register can be programmed with these steps:
Figure 47 and Table 4 show the timing requirements for the serial register write operation.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDIO setup time | 25 | ns | ||
tDH | SDIO hold time | 25 | ns |