The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC342x | VQFN (56) | 8.00 mm × 8.00 mm |
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PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 6, 7, 10, 11, 14, 15, 20, 23, 28, 29, 32, 33, 36 | I | Analog 1.8-V power supply |
CLKM | 21 | I | Negative differential clock input for the ADC |
CLKP | 22 | I | Positive differential clock input for the ADC |
DA0M | 4 | O | Negative serial LVDS output for wire-0 of channel A |
DA0P | 3 | O | Positive serial LVDS output for wire-0 of channel A |
DA1M | 2 | O | Negative serial LVDS output for wire-1 of channel A |
DA1P | 1 | O | Positive serial LVDS output for wire-1 of channel A |
DB0M | 56 | O | Negative serial LVDS output for wire-0 of channel B |
DB0P | 55 | O | Positive serial LVDS output for wire-0 of channel B |
DB1M | 54 | O | Negative serial LVDS output for wire-1 of channel B |
DB1P | 53 | O | Positive serial LVDS output for wire-1 of channel B |
DC0M | 46 | O | Negative serial LVDS output for wire-0 of channel C |
DC0P | 45 | O | Positive serial LVDS output for wire-0 of channel C |
DC1M | 44 | O | Negative serial LVDS output for wire-1 of channel C |
DC1P | 43 | O | Positive serial LVDS output for wire-1 of channel C |
DD0M | 42 | O | Negative serial LVDS output for wire-0 of channel D |
DD0P | 41 | O | Positive serial LVDS output for wire-0 of channel D |
DD1M | 40 | O | Negative serial LVDS output for wire-1 of channel D |
DD1P | 39 | O | Positive serial LVDS output for wire-1 of channel D |
DCLKM | 51 | O | Negative bit clock output |
DCLKP | 50 | O | Positive bit clock output |
DVDD | 5, 38, 47, 52 | I | Digital 1.8-V power supply |
FCLKM | 49 | O | Negative frame clock output |
FCLKP | 48 | O | Positive frame clock output |
GND | PowerPAD™ | I | Ground, 0 V |
INAM | 8 | I | Negative differential analog input for channel A |
INAP | 9 | I | Positive differential analog input for channel A |
INBM | 13 | I | Negative differential analog input for channel B |
INBP | 12 | I | Positive differential analog input for channel B |
INCM | 30 | I | Negative differential analog input for channel C |
INCP | 31 | I | Positive differential analog input for channel C |
INDM | 35 | I | Negative differential analog input for channel D |
INDP | 34 | I | Positive differential analog input for channel D |
PDN | 37 | I | Power-down control. This pin can be configured via the SPI. This pin has an internal 150-kΩ pulldown resistor. |
RESET | 24 | I | Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. |
SCLK | 16 | I | Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. |
SDATA | 17 | I | Serial interface data input. This pin has an internal 150-kΩ pulldown resistor. |
SDOUT | 19 | O | Serial interface data output |
SEN | 18 | I | Serial interface enable; active low. This pin has an internal 150-kΩ pullup resistor to AVDD. |
SYSREFM | 26 | I | Negative external SYSREF input |
SYSREFP | 25 | I | Positive external SYSREF input |
VCM | 27 | O | Common-mode voltage for analog inputs |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Analog supply voltage range, AVDD | –0.3 | 2.1 | V | |
Digital supply voltage range, DVDD | –0.3 | 2.1 | V | |
Voltage applied to input pins |
INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM | –0.3 | min (1.9, AVDD + 0.3) | V |
CLKP, CLKM | –0.3 | AVDD + 0.3 | ||
SYSREFP, SYSREFM | –0.3 | AVDD + 0.3 | ||
SCLK, SEN, SDATA, RESET, PDN | –0.3 | 3.9 | ||
Temperature | Operating free-air, TA | –40 | 85 | ºC |
Operating junction, TJ | 125 | |||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLIES | ||||||
AVDD | Analog supply voltage range | 1.7 | 1.8 | 1.9 | V | |
DVDD | Digital supply voltage range | 1.7 | 1.8 | 1.9 | V | |
ANALOG INPUT | ||||||
VID | Differential input voltage | For input frequencies < 450 MHz | 2 | VPP | ||
For input frequencies < 600 MHz | 1 | |||||
VIC | Input common-mode voltage | VCM ± 0.025 | V | |||
CLOCK INPUT | ||||||
Input clock frequency | Sampling clock frequency | 15(2) | 125(1) | MSPS | ||
Input clock amplitude (differential) | Sine wave, ac-coupled | 0.2 | 1.5 | VPP | ||
LPECL, ac-coupled | 1.6 | |||||
LVDS, ac-coupled | 0.7 | |||||
Input clock duty cycle | 35% | 50% | 65% | |||
Input clock common-mode voltage | 0.95 | V | ||||
DIGITAL OUTPUTS | ||||||
CLOAD | Maximum external load capacitance from each output pin to GND | 3.3 | pF | |||
RLOAD | Single-ended load resistance | 100 | Ω |
THERMAL METRIC(1) | ADC342x | UNIT | |
---|---|---|---|
RTQ (VQFN) | |||
56 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 25.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 9.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 3.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 3.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ANALOG INPUT | |||||||
Differential input full-scale | 2.0 | VPP | |||||
ri | Input resistance | Differential at dc | 6.6 | kΩ | |||
ci | Input capacitance | Differential at dc | 3.7 | pF | |||
VOC(VCM) | VCM common-mode voltage output | 0.95 | V | ||||
VCM output current capability | 10 | mA | |||||
Input common-mode current | Per analog input pin | 1.5 | µA/MSPS | ||||
Analog input bandwidth (3 dB) | 50-Ω differential source driving 50-Ω termination across INP and INM | 540 | MHz | ||||
DC ACCURACY | |||||||
EO | Offset error | –25 | 25 | mV | |||
αEO | Temperature coefficient of offset error | ± 0.024 | mV/°C | ||||
EG(REF) | Gain error as a result of internal reference inaccuracy alone | –2 | 2 | %FS | |||
EG(CHAN) | Gain error of channel alone | –2 | %FS | ||||
α(EGCHAN) | Temperature coefficient of EG(CHAN) | ±0.008 | Δ%FS/Ch | ||||
CHANNEL-TO-CHANNEL ISOLATION | |||||||
Crosstalk(1) | fIN = 10 MHz | Near channel | 105 | dB | |||
Far channel | 105 | ||||||
fIN = 100 MHz | Near channel | 95 | |||||
Far channel | 105 | ||||||
fIN = 200 MHz | Near channel | 94 | |||||
Far channel | 105 | ||||||
fIN = 230 MHz | Near channel | 92 | |||||
Far channel | 105 | ||||||
fIN = 300 MHz | Near channel | 85 | |||||
Far channel | 105 |
PARAMETER | ADC3421 | ADC3422 | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||
ADC clock frequency | 25 | 50 | MSPS | |||||
Resolution | 12 | 12 | Bits | |||||
1.8-V analog supply current | 54 | 71 | 71 | 90 | mA | |||
1.8-V digital supply current | 45 | 71 | 56 | 90 | mA | |||
Total power dissipation | 177 | 240 | 228 | 305 | mW | |||
Global power-down dissipation | 5 | 17 | 5 | 17 | mW | |||
Standby power-down dissipation | 34 | 75 | 35 | 75 | mW |
PARAMETER | ADC3423 | ADC3424 | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||
ADC clock frequency | 80 | 125 | MSPS | |||||
Resolution | 12 | 12 | Bits | |||||
1.8-V analog supply current | 92 | 107 | 119 | 145 | mA | |||
1.8-V digital supply current | 68 | 100 | 98 | 145 | mA | |||
Total power dissipation | 288 | 365 | 391 | 475 | mW | |||
Global power-down dissipation | 5 | 17 | 5 | 17 | mW | |||
Standby power-down dissipation | 40 | 88 | 43 | 103 | mW |
PARAMETER | TEST CONDITIONS | ADC3421 (fS = 25 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
SNR | Signal-to-noise ratio (from 1-MHz offset) |
fIN = 10 MHz | 70.9 | 71.1 | dBFS | ||||
fIN = 20 MHz | 68.9 | 70.7 | 70.9 | ||||||
fIN = 70 MHz | 70.4 | 70.6 | |||||||
fIN = 100 MHz | 70.3 | 70.5 | |||||||
fIN = 170 MHz | 69.7 | 69.9 | |||||||
fIN = 230 MHz | 68.9 | 69.1 | |||||||
Signal-to-noise ratio (full Nyquist band) |
fIN = 10 MHz | 70.2 | 70.5 | dBFS | |||||
fIN = 20 MHz | 70.1 | 70.3 | |||||||
fIN = 70 MHz | 69.8 | 70.0 | |||||||
fIN = 100 MHz | 69.6 | 69.8 | |||||||
fIN = 170 MHz | 69.2 | 69.3 | |||||||
fIN = 230 MHz | 68.3 | 68.5 | |||||||
NSD(1) | Noise spectral density (averaged across Nyquist zone) | fIN = 10 MHz | –141.5 | –141.7 | dBFS/Hz | ||||
fIN = 20 MHz | –141.3 | –139.5 | –141.5 | ||||||
fIN = 70 MHz | –141.0 | –141.2 | |||||||
fIN = 100 MHz | –140.9 | –141.1 | |||||||
fIN = 170 MHz | –140.3 | –140.5 | |||||||
fIN = 230 MHz | –139.5 | –139.7 | |||||||
SINAD(1) | Signal-to-noise and distortion ratio | fIN = 10 MHz | 71 | 71.1 | dBFS | ||||
fIN = 20 MHz | 67.9 | 70.8 | 70.9 | ||||||
fIN = 70 MHz | 69.5 | 70 | |||||||
fIN = 100 MHz | 70.5 | 70.7 | |||||||
fIN = 170 MHz | 69.6 | 69.8 | |||||||
fIN = 230 MHz | 68.7 | 68.7 | |||||||
ENOB(1) | Effective number of bits | fIN = 10 MHz | 11.5 | 11.5 | Bits | ||||
fIN = 20 MHz | 11 | 11.4 | 11.4 | ||||||
fIN = 70 MHz | 11.4 | 11.4 | |||||||
fIN = 100 MHz | 11.4 | 11.4 | |||||||
fIN = 170 MHz | 11.3 | 11.3 | |||||||
fIN = 230 MHz | 11.1 | 11.1 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 93 | 90 | dBc | ||||
fIN = 20 MHz | 84 | 91 | 85 | ||||||
fIN = 70 MHz | 93 | 88 | |||||||
fIN = 100 MHz | 85 | 82 | |||||||
fIN = 170 MHz | 86 | 85 | |||||||
fIN = 230 MHz | 82 | 82 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 93 | 92 | dBc | ||||
fIN = 20 MHz | 84 | 100 | 94 | ||||||
fIN = 70 MHz | 93 | 92 | |||||||
fIN = 100 MHz | 94 | 93 | |||||||
fIN = 170 MHz | 86 | 85 | |||||||
fIN = 230 MHz | 86 | 82 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 96 | 90 | dBc | ||||
fIN = 20 MHz | 84 | 91 | 85 | ||||||
fIN = 70 MHz | 93 | 88 | |||||||
fIN = 100 MHz | 85 | 82 | |||||||
fIN = 170 MHz | 89 | 89 | |||||||
fIN = 230 MHz | 82 | 82 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 99 | 92 | dBc | ||||
fIN = 20 MHz | 87 | 98 | 91 | ||||||
fIN = 70 MHz | 96 | 92 | |||||||
fIN = 100 MHz | 95 | 93 | |||||||
fIN = 170 MHz | 92 | 90 | |||||||
fIN = 230 MHz | 97 | 91 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 90 | 86 | dBc | ||||
fIN = 20 MHz | 81 | 90 | 83 | ||||||
fIN = 70 MHz | 89 | 85 | |||||||
fIN = 100 MHz | 84 | 80 | |||||||
fIN = 170 MHz | 84 | 83 | |||||||
fIN = 230 MHz | 80 | 79 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
–98 | –98 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
–91 | –91 |
PARAMETER | TEST CONDITIONS | ADC3422 (fS = 50 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
SNR | Signal-to-noise ratio (from 1-MHz offset) |
fIN = 10 MHz | 70.8 | 71 | dBFS | ||||
fIN = 20 MHz | 68.9 | 70.6 | 70.8 | ||||||
fIN = 70 MHz | 70.5 | 70.7 | |||||||
fIN = 100 MHz | 70.4 | 70.6 | |||||||
fIN = 170 MHz | 69.8 | 70.1 | |||||||
fIN = 230 MHz | 68.8 | 69 | |||||||
Signal-to-noise ratio (full Nyquist band) |
fIN = 10 MHz | 70.2 | 70.4 | ||||||
fIN = 20 MHz | 69.8 | 70.0 | |||||||
fIN = 70 MHz | 69.7 | 69.9 | |||||||
fIN = 100 MHz | 69.8 | 70.1 | |||||||
fIN = 170 MHz | 69.3 | 69.5 | |||||||
fIN = 230 MHz | 68.2 | 68.4 | |||||||
NSD(1) | Noise spectral density (averaged across Nyquist zone) | fIN = 10 MHz | –144.6 | –144.8 | dBFS/Hz | ||||
fIN = 20 MHz | –144.4 | –142.7 | –144.6 | ||||||
fIN = 70 MHz | –144.3 | –144.5 | |||||||
fIN = 100 MHz | –144.2 | –144.4 | |||||||
fIN = 170 MHz | –143.6 | –143.9 | |||||||
fIN = 230 MHz | –142.6 | –142.8 | |||||||
SINAD(1) | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.8 | 71 | dBFS | ||||
fIN = 20 MHz | 67.9 | 70.7 | 70.9 | ||||||
fIN = 70 MHz | 70.3 | 70.6 | |||||||
fIN = 100 MHz | 70.6 | 70.8 | |||||||
fIN = 170 MHz | 69.7 | 69.9 | |||||||
fIN = 230 MHz | 68.6 | 68.8 | |||||||
ENOB(1) | Effective number of bits | fIN = 10 MHz | 11.5 | 11.5 | Bits | ||||
fIN = 20 MHz | 11 | 11.4 | 11.5 | ||||||
fIN = 70 MHz | 11.4 | 11.5 | |||||||
fIN = 100 MHz | 11.4 | 11.5 | |||||||
fIN = 170 MHz | 11.3 | 11.3 | |||||||
fIN = 230 MHz | 11.1 | 11.1 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 90 | 92 | dBc | ||||
fIN = 20 MHz | 82 | 95 | 90 | ||||||
fIN = 70 MHz | 93 | 92 | |||||||
fIN = 100 MHz | 87 | 87 | |||||||
fIN = 170 MHz | 87 | 86 | |||||||
fIN = 230 MHz | 83 | 83 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 95 | 92 | dBc | ||||
fIN = 20 MHz | 83 | 98 | 95 | ||||||
fIN = 70 MHz | 93 | 92 | |||||||
fIN = 100 MHz | 94 | 92 | |||||||
fIN = 170 MHz | 87 | 86 | |||||||
fIN = 230 MHz | 85 | 83 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 90 | 92 | dBc | ||||
fIN = 20 MHz | 82 | 94 | 92 | ||||||
fIN = 70 MHz | 94 | 92 | |||||||
fIN = 100 MHz | 87 | 87 | |||||||
fIN = 170 MHz | 88 | 89 | |||||||
fIN = 230 MHz | 83 | 88 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 99 | 93 | dBc | ||||
fIN = 20 MHz | 87 | 99 | 93 | ||||||
fIN = 70 MHz | 98 | 92 | |||||||
fIN = 100 MHz | 95 | 94 | |||||||
fIN = 170 MHz | 96 | 89 | |||||||
fIN = 230 MHz | 96 | 90 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 88 | 87 | dBc | ||||
fIN = 20 MHz | 79 | 89 | 89 | ||||||
fIN = 70 MHz | 90 | 87 | |||||||
fIN = 100 MHz | 86 | 85 | |||||||
fIN = 170 MHz | 84 | 83 | |||||||
fIN = 230 MHz | 81 | 81 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
–95 | –95 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
–88 | –88 |
PARAMETER | TEST CONDITIONS | ADC3423 (fS = 80 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
SNR | Signal-to-noise ratio (from 1-MHz offset) |
fIN = 10 MHz | 70.7 | 70.9 | dBFS | ||||
fIN = 70 MHz | 68.7 | 70.5 | 70.7 | ||||||
fIN = 100 MHz | 70.3 | 70.5 | |||||||
fIN = 170 MHz | 70.1 | 70.3 | |||||||
fIN = 230 MHz | 69.6 | 69.9 | |||||||
Signal-to-noise ratio (full Nyquist band) |
fIN = 10 MHz | 70.3 | 70.5 | ||||||
fIN = 70 MHz | 70.1 | 70.4 | |||||||
fIN = 100 MHz | 69.9 | 70.2 | |||||||
fIN = 170 MHz | 69.7 | 69.9 | |||||||
fIN = 230 MHz | 69.3 | 69.6 | |||||||
NSD(1) | Noise spectral density (averaged across Nyquist zone) | fIN = 10 MHz | –146.6 | –146.8 | dBFS/Hz | ||||
fIN = 70 MHz | –146.4 | –144.6 | –146.6 | ||||||
fIN = 100 MHz | –146.2 | –146.4 | |||||||
fIN = 170 MHz | –146.0 | –146.2 | |||||||
fIN = 230 MHz | –145.5 | –145.8 | |||||||
SINAD(1) | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.7 | 70.8 | dBFS | ||||
fIN = 70 MHz | 67.7 | 70.3 | 70.4 | ||||||
fIN = 100 MHz | 70.4 | 70.7 | |||||||
fIN = 170 MHz | 70 | 70.2 | |||||||
fIN = 230 MHz | 69.5 | 69.7 | |||||||
ENOB(1) | Effective number of bits | fIN = 10 MHz | 11.5 | 11.5 | Bits | ||||
fIN = 70 MHz | 11 | 11.4 | 11.4 | ||||||
fIN = 100 MHz | 11.4 | 11.5 | |||||||
fIN = 170 MHz | 11.3 | 11.4 | |||||||
fIN = 230 MHz | 11.3 | 11.3 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 90 | 90 | dBc | ||||
fIN = 70 MHz | 81 | 91 | 90 | ||||||
fIN = 100 MHz | 93 | 93 | |||||||
fIN = 170 MHz | 88 | 86 | |||||||
fIN = 230 MHz | 87 | 85 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 94 | 91 | dBc | ||||
fIN = 70 MHz | 81 | 96 | 92 | ||||||
fIN = 100 MHz | 97 | 93 | |||||||
fIN = 170 MHz | 88 | 86 | |||||||
fIN = 230 MHz | 87 | 85 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 90 | 90 | dBc | ||||
fIN = 70 MHz | 81 | 91 | 90 | ||||||
fIN = 100 MHz | 93 | 99 | |||||||
fIN = 170 MHz | 96 | 93 | |||||||
fIN = 230 MHz | 87 | 87 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 99 | 94 | dBc | ||||
fIN = 70 MHz | 86 | 98 | 93 | ||||||
fIN = 100 MHz | 94 | 94 | |||||||
fIN = 170 MHz | 95 | 92 | |||||||
fIN = 230 MHz | 94 | 91 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 88 | 86 | dBc | ||||
fIN = 70 MHz | 78 | 89 | 86 | ||||||
fIN = 100 MHz | 91 | 90 | |||||||
fIN = 170 MHz | 87 | 84 | |||||||
fIN = 230 MHz | 84 | 82 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
–97 | –97 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
–92 | –92 |
PARAMETER | TEST CONDITIONS | ADC3424 (fS = 125 MSPS) | UNIT | ||||||
---|---|---|---|---|---|---|---|---|---|
DITHER ON | DITHER OFF | ||||||||
MIN | TYP | MAX | MIN | TYP | MAX | ||||
SNR | Signal-to-noise ratio (from 1-MHz offset) |
fIN = 10 MHz | 70.5 | 70.7 | dBFS | ||||
fIN = 70 MHz | 68 | 70.3 | 70.6 | ||||||
fIN = 100 MHz | 70.1 | 70.4 | |||||||
fIN = 170 MHz | 69.8 | 70.3 | |||||||
fIN = 230 MHz | 69.2 | 69.9 | |||||||
Signal-to-noise ratio (full Nyquist band) |
fIN = 10 MHz | 70.3 | 70.5 | ||||||
fIN = 70 MHz | 70.1 | 70.4 | |||||||
fIN = 100 MHz | 70.0 | 70.2 | |||||||
fIN = 170 MHz | 69.6 | 70.1 | |||||||
fIN = 230 MHz | 69.0 | 69.7 | |||||||
NSD(1) | Noise spectral density (averaged across Nyquist zone) | fIN = 10 MHz | –148.4 | –148.6 | dBFS/Hz | ||||
fIN = 70 MHz | –148.2 | –145.9 | –148.5 | ||||||
fIN = 100 MHz | –148.0 | –148.3 | |||||||
fIN = 170 MHz | –147.7 | –148.2 | |||||||
fIN = 230 MHz | –147.1 | –147.8 | |||||||
SINAD(1) | Signal-to-noise and distortion ratio | fIN = 10 MHz | 70.5 | 70.6 | dBFS | ||||
fIN = 70 MHz | 67 | 70.3 | 70.5 | ||||||
fIN = 100 MHz | 70.1 | 70.5 | |||||||
fIN = 170 MHz | 69.7 | 70.1 | |||||||
fIN = 230 MHz | 68.6 | 69.1 | |||||||
ENOB(1) | Effective number of bits | fIN = 10 MHz | 11.4 | 11.4 | Bits | ||||
fIN = 70 MHz | 10.8 | 11.4 | 11.4 | ||||||
fIN = 100 MHz | 11.4 | 11.4 | |||||||
fIN = 170 MHz | 11.3 | 11.4 | |||||||
fIN = 230 MHz | 11.2 | 11.3 | |||||||
SFDR | Spurious-free dynamic range | fIN = 10 MHz | 93 | 89 | dBc | ||||
fIN = 70 MHz | 80 | 94 | 90 | ||||||
fIN = 100 MHz | 90 | 87 | |||||||
fIN = 170 MHz | 86 | 85 | |||||||
fIN = 230 MHz | 81 | 80 | |||||||
HD2 | Second-order harmonic distortion | fIN = 10 MHz | 93 | 92 | dBc | ||||
fIN = 70 MHz | 80 | 94 | 91 | ||||||
fIN = 100 MHz | 90 | 91 | |||||||
fIN = 170 MHz | 86 | 85 | |||||||
fIN = 230 MHz | 81 | 80 | |||||||
HD3 | Third-order harmonic distortion | fIN = 10 MHz | 96 | 88 | dBc | ||||
fIN = 70 MHz | 81 | 95 | 89 | ||||||
fIN = 100 MHz | 97 | 90 | |||||||
fIN = 170 MHz | 93 | 87 | |||||||
fIN = 230 MHz | 87 | 86 | |||||||
Non HD2, HD3 |
Spurious-free dynamic range (excluding HD2, HD3) | fIN = 10 MHz | 100 | 93 | dBc | ||||
fIN = 70 MHz | 86 | 99 | 94 | ||||||
fIN = 100 MHz | 94 | 93 | |||||||
fIN = 170 MHz | 95 | 92 | |||||||
fIN = 230 MHz | 94 | 90 | |||||||
THD | Total harmonic distortion | fIN = 10 MHz | 90 | 85 | dBc | ||||
fIN = 70 MHz | 77 | 90 | 85 | ||||||
fIN = 100 MHz | 88 | 86 | |||||||
fIN = 170 MHz | 85 | 82 | |||||||
fIN = 230 MHz | 80 | 78 | |||||||
IMD3 | Two-tone, third-order intermodulation distortion | fIN1 = 45 MHz, fIN2 = 50 MHz |
95 | 95 | dBFS | ||||
fIN1 = 185 MHz, fIN2 = 190 MHz |
89 | 89 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN) | |||||||
VIH | High-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | 1.3 | V | |||
VIL | Low-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | 0.4 | V | |||
IIH | High-level input current | RESET, SDATA, SCLK, PDN | VHIGH = 1.8 V | 10 | µA | ||
SEN(1) | VHIGH = 1.8 V | 0 | µA | ||||
IIL | Low-level input current | RESET, SDATA, SCLK, PDN | VLOW = 0 V | 0 | µA | ||
SEN | VLOW = 0 V | 10 | µA | ||||
DIGITAL INPUTS (SYSREFP, SYSREFM) | |||||||
VIH | High-level input voltage | 1.3 | V | ||||
VIL | Low-level input voltage | 0.5 | V | ||||
Common-mode voltage for SYSREF | 0.9 | V | |||||
DIGITAL OUTPUTS (CMOS Interface, SDOUT) | |||||||
VOH | High-level output voltage | DVDD – 0.1 | DVDD | V | |||
VOL | Low-level output voltage | 0 | 0.1 | V | |||
DIGITAL OUTPUTS (LVDS Interface) | |||||||
VODH | High-level output differential voltage | With an external 100-Ω termination | 280 | 350 | 460 | mV | |
VODL | Low-level output differential voltage | With an external 100-Ω termination | –460 | –350 | –280 | mV | |
VOCM | Output common-mode voltage | 1.05 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
tA | Aperture delay | 1.24 | 1.44 | 1.64 | ns | |
Aperture delay matching between two channels of the same device | ±70 | ps | ||||
Aperture delay variation between two devices at same temperature and supply voltage | ±150 | ps | ||||
tJ | Aperture jitter | 130 | fS rms | |||
Wake-up time: | Time to valid data after exiting standby power-down mode | 35 | 200 | µs | ||
Time to valid data after exiting global power-down mode (in this mode, both channels power down) |
85 | 450 | µs | |||
ADC latency(6): | 2-wire mode (default) | 9 | Clock cycles | |||
1-wire mode | 8 | Clock cycles | ||||
tSU_SYSREF | SYSREF reference time: | Setup time for SYSREF referenced to input clock rising edge | 1000 | ps | ||
tH_SYSREF | Hold time for SYSREF referenced to input clock rising edge | 100 | ps |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
tSU | Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)(5) | 0.43 | 0.5 | ns | ||
tHO | Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid(5) |
0.48 | 0.58 | ns | ||
tPDI | Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over (15 MSPS < sampling frequency < 125 MSPS) |
1-wire mode | 2.7 | 4.5 | 6.5 | ns |
2-wire mode | 0.44 × tS + tDELAY | ns | ||||
tDELAY | Delay time | 3 | 4.5 | 5.9 | ns | |
LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) |
49% | |||||
tFALL, tRISE |
Data fall time, data rise time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS |
0.11 | ns | |||
tCLKRISE, tCLKFALL |
Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS |
0.11 | ns |
SAMPLING FREQUENCY (MSPS) |
SETUP TIME (tSU, ns) |
HOLD TIME (tHO, ns) |
||||
---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |
25 | 2.61 | 3.06 | 2.75 | 3.12 | ||
40 | 1.69 | 1.9 | 1.8 | 1.98 | ||
60 | 1.11 | 1.23 | 1.18 | 1.31 | ||
80 | 0.81 | 0.89 | 0.88 | 0.97 | ||
100 | 0.6 | 0.68 | 0.68 | 0.77 |
SAMPLING FREQUENCY (MSPS) |
SETUP TIME (tSU, ns) |
HOLD TIME (tHO, ns) |
||||
---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |
25 | 1.3 | 1.48 | 1.32 | 1.57 | ||
40 | 0.76 | 0.88 | 0.79 | 0.97 | ||
50 | 0.57 | 0.68 | 0.61 | 0.77 | ||
60 | 0.42 | 0.55 | 0.45 | 0.62 | ||
70 | 0.35 | 0.44 | 0.4 | 0.51 | ||
80 | 0.26 | 0.35 | 0.35 | 0.43 |
SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS, THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc |
SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.3 dBFS, THD = 91 dBc, HD2 = 105 dBc, HD3 = 92 dBc |
SFDR = 87 dBc, SNR = 69.8 dBFS, SINAD = 69.7 dBFS, THD = 85 dBc, HD2 = 90 dBc, HD3 = 87 dBc |
SFDR = 77 dBc, SNR = 68.2 dBFS, SINAD = 67.7 dBFS, THD = 75 dBc, HD2 = 77 dBc, HD3 = 83 dBc |
SFDR = 67 dBc, SNR = 66.4 dBFS, SINAD = 66.4 dBFS, THD = 93 dBc, HD2 = 67 dBc, HD3 = 88 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90, each tone at = –7 dBFS |
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 91, each tone at = –7 dBFS |
SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS, THD = 89 dBc, HD2 = 90 dBc, HD3 = 106 dBc |
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 88 dBc, HD2 = 91 dBc, HD3 = 101 dBc |
SFDR = 85 dBc, SNR = 70 dBFS, SINAD = 69.8 dBFS, THD = 86 dBc, HD2 = 85 dBc, HD3 = 92 dBc |
SFDR = 75 dBc, SNR = 68.4 dBFS, SINAD = 67.5 dBFS, THD = 74 dBc, HD2 = 75 dBc, HD3 = 80 dBc |
SFDR = 66 dBc, SNR = 66.5 dBFS, SINAD = 66.5 dBFS, THD = 87 dBc, HD2 = 66 dBc, HD3 = 93 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105, each tone at = –36 dBFS |
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 98 dBFS, each tone at –36 dBFS |
SFDR = 89 dBc, SNR = 70.9 dBFS, SINAD = 70.8 dBFS, THD = 88 dBc, HD2 = 110 dBc, HD3 = 89 dBc |
SFDR = 101 dBc, SNR = 70.6 dBFS, SINAD = 70.5 dBFS, THD = 98 dBc, HD2 = 106 dBc, HD3 = 101 dBc |
SFDR = 86 dBc, SNR = 69.9 dBFS, SINAD = 69.8 dBFS, THD = 85 dBc, HD2 = 93 dBc, HD3 = 86 dBc |
SFDR = 75 dBc, SNR = 69 dBFS, SINAD = 67.9 dBFS, THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc |
SFDR = 68 dBc, SNR = 67.2 dBFS, SINAD = 67.1 dBFS, THD = –86 dBc, HD2 = 75 dBc, HD3 = 73 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 102 dBFS, each tone at –7 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 95 dBFS, each tone at –7 dBFS |
SFDR = 85 dBc, SNR = 71.2 dBFS, SINAD = 70.9 dBFS, THD = 83 dBc, HD2 = 92 dBc, HD3 = 85 dBc |
SFDR = 90 dBc, SNR = 70.8 dBFS, SINAD = 70.6 dBFS, THD = 87 dBc, HD2 = 91 dBc, HD3 = 90 dBc |
SFDR = 85 dBc, SNR = 70.1 dBFS, SINAD = 70 dBFS, THD = 86 dBc, HD2 = 85 dBc ,HD3 = 112 dBc |
SFDR = 75 dBc, SNR = 69.2 dBFS, SINAD = 67.9 dBFS, THD = 73 dBc, HD2 = 75 dBc, HD3 = 81 dBc |
SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.4 dBFS, THD = –87 dBc, HD2 = –68 dBc, HD3 = –87 dBc |
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 110 dBFS, each tone at –36 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS, each tone at –36 dBFS |
SFDR = 89 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 89 dBc, HD2 = 108 dBc, HD3 = 89 dBc |
SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS, THD = 91 dBc, HD2 = 112 dBc, HD3 = 92 dBc |
SFDR = 87 dBc, SNR = 70.2 dBFS, SINAD = 70.1 dBFS, THD = 93 dBc, HD2 = 102 dBc, HD3 = 87 dBc |
SFDR = 76 dBc, SNR = 69.2 dBFS, SINAD = 68.3 dBFS, THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc |
SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.1 dBFS, THD = 77 dBc, HD2 = 68 dBc, HD3 = 89 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 98 dBFS, each tone at –7 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 90 dBFS, each tone at –7 dBFS |
SFDR = 84 dBc, SNR = 70.9 dBFS, SINAD = 70.7 dBFS, THD = 83 dBc, HD2 = 92 dBc, HD3 = 84 dBc |
SFDR = 86 dBc, SNR = 70.7 dBFS, SINAD = 70.5 dBFS, THD = 84 dBc, HD2 = 92 dBc, HD3 = 86 dBc |
SFDR = 86 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS, THD = 88 dBc, HD2 = 86 dBc, HD3 = 97 dBc |
SFDR = 75 dBc, SNR = 69.5 dBFS, SINAD = 68.4 dBFS, THD = 75 dBc, HD2 = 75 dBc, HD3 = 82 dBc |
SFDR = 67 dBc SNR = 67.7 dBFS, SINAD = 67.3 dBFS, THD = 77 dBc, HD2 = 67 dBc, HD3 = 84 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS, each tone at –36 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS, each tone at –36 dBFS |
SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc |
SFDR = 99 dBc, SNR = 70.3 dBFS, SINAD = 70.3 dBFS, THD = 95 dBc, HD2 = 103 dBc, HD3 = 99 dBc |
SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS, THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc |
SFDR = 76 dBc, SNR = 68.94 dBFS, SINAD = 68.4 dBFS, THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc |
SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS, THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 100 dBFS, each tone at –7 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86 dBFS, each tone at –7 dBFS |
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc |
SFDR = 91 dBc, SNR = 70.6 dBFS, SINAD = 70.6 dBFS, THD = 87 dBc, HD2 = 91 dBc, HD3 = 95 dBc |
SFDR = 85 dBc, SNR = 70.3 dBFS, SINAD = 70.2 dBFS, THD = 88 dBc, HD2 = 99 dBc, HD3 = 85 dBc |
SFDR = 76 dBc, SNR = 69.3 dBFS, SINAD = 68.6 dBFS, THD = 75 dBc, HD2 = 76 dBc, HD3 = 82 dBc |
SFDR = 69 dBc, SNR = 67.8 dBFS, SINAD = 66.8 dBFS, THD = 73 dBc, HD2 = 77 dBc, HD3 = 69 dBc |
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 99 dBFS, each tone at –36 dBFS |
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 102 dBFS, each tone at –36 dBFS |
fIN = 30 MHz, AIN = –1 dBFS, test signal amplitude = 50 mVPP |
fIN = 30 MHz, AIN = –1 dBFS, test signal amplitude = 50 mVPP |
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP, SINAD = 58.51 dBFS, SFDR = 60 dBc |
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP, SINAD = 69.66 dBFS, SFDR = 75 dBc |
The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports a serial low-voltage differential signaling (LVDS) interface in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The ADC342x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω termination between INP and INM).
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC342x can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 132, Figure 133, and Figure 134. See Figure 135 for details regarding the internal clock buffer.
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 136. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 74 dB for a 12-bit ADC) and thermal noise limit SNR at low input frequencies, and the clock jitter sets SNR for higher input frequencies.
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.
The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device) which is set by the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3.
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input; a faster clock slew rate improves the ADC aperture jitter. The devices have a typical thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 137.
The devices offer two different output format options, thus making interfacing to a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using the serial interface, as shown in Table 3. The output interface options are:
INTERFACE OPTIONS | SERIALIZATION | RECOMMENDED SAMPLING FREQUENCY (MSPS) | BIT CLOCK FREQUENCY (MHz) | FRAME CLOCK FREQUENCY (MHz) | SERIAL DATA RATE PER WIRE (Mbps) | |
---|---|---|---|---|---|---|
MINIMUM | MAXIMUM | |||||
One-wire | 12x | 15 | 90 | 15 | 180 | |
80 | 480 | 80 | 960 | |||
Two-wire (Default after Reset) |
6x | 20(1) | 60 | 20 | 120 | |
125 | 375 | 125 | 750 |
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x serialization).
The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 6x sample frequency because six data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the six MSBs on Dx1P, Dx1M and the six LSBs on Dx0P, Dx0M, as shown in Figure 138.
The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for operation with a 125-MHz clock and the divide-by-2 option supports a maximum input clock of 250 MHz and the divide-by-4 option provides a maximum input clock frequency of 500 MHz.
The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 139 shows the noise spectrum with the chopper off and Figure 140 shows the noise spectrum with the chopper on. This function is especially useful in applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function creates a spur at fS / 2 that must be filtered out digitally.
fS = 125 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 98 dBc |
fS = 125 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 97 dBc |
The power-down functions of the ADC342x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-down or standby functionality, as shown in Table 4.
FUNCTION | POWER CONSUMPTION (mW) | WAKE-UP TIME (µs) |
---|---|---|
Global power-down | 5 | 85 |
Standby | 45 | 35 |
The ADC342x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 141 and Figure 142 show the effect of using dither algorithms.
SFDR = 95 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc |
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc |
Table 5 lists the location, value, and functions of performance mode registers in the device.
MODE | REGISTER SETTINGS | DESCRIPTION |
---|---|---|
Special modes | Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3) | Always write 1 for best performance |
Disable dither | Registers 1 (bits 7:0), 134 (bits 5 and 3), 234 (bits 5 and 3), 434 (bits 5 and 3), and 534 (bits 5 and 3) |
Disable dither to improve SNR |
Disable chopper | Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1) | Disable chopper (shifts 1/f noise floor at dc) |
High IF modes | Registers 11Dh (bit 1), 21Dh (bit 1), 41Dh (bit 1), 51Dh (bit 1), 308h (bits 7-6) and 608h (bits 7-6) | Improves HD3 by a couple of dB for IF > 100 MHz |
The ADC342x can be configured using a serial programming interface, as described in this section.
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 143. If required, the serial interface registers can be cleared during operation either:
The device internal register can be programmed with these steps:
Figure 143 and Table 6 show the timing requirements for the serial register write operation.
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency (equal to 1 / tSCLK) | > dc | 20 | MHz | |
tSLOADS | SEN to SCLK setup time | 25 | ns | ||
tSLOADH | SCLK to SEN hold time | 25 | ns | ||
tDSU | SDIO setup time | 25 | ns | ||
tDH | SDIO hold time | 25 | ns |
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 144 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 145.
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 146 and Table 7.
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
t1 | Power-on delay from power-up to active high RESET pulse | 1 | ms | |||
t2 | Reset pulse duration: active high RESET pulse duration | 10 | ns | |||
t3 | Register write delay from RESET disable to SEN active | 100 | ns |
If required, the serial interface registers can be cleared during operation either:
REGISTER ADDRESS, A[13:0] (Hex) | REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Register 01h | DIS DITH CHA | DIS DITH CHB | DIS DITH CHC | DIS DITH CHD | ||||
Register 03h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ODD EVEN |
Register 04h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FLIP WIRE |
Register 05h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1W-2W |
Register 06h | 0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
Register 07h | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OVR ON LSB |
Register 09h | 0 | 0 | 0 | 0 | 0 | 0 | ALIGN TEST PATTERN | DATA FORMAT |
Register 0Ah | CHA TEST PATTERN | CHB TEST PATTERN | ||||||
Register 0Bh | CHC TEST PATTERN 0 | CHD TEST PATTERN | ||||||
Register 0Eh | CUSTOM PATTERN[11:4] | |||||||
Register 0Fh | CUSTOM PATTERN[3:0] | 0 | 0 | 0 | 0 | |||
Register 13h | 0 | 0 | 0 | 0 | 0 | 0 | LOW SPEED ENABLE | |
Register 15h | CHA PDN | CHB PDN | CHC PDN | CHD PDN | STANDBY | GLOBAL PDN | 0 | CONFIG PDN PIN |
Register 25h | LVDS SWING | |||||||
Register 27h | CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 11Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE0 | 0 |
Register 122h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHA | 0 |
Register 134h | 0 | 0 | DIS DITH CHA | 0 | DIS DITH CHA | 0 | 0 | 0 |
Register 139h | 0 | 0 | 0 | 0 | SP1 CHA | 0 | 0 | 0 |
Register 21Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE1 | 0 |
Register 222h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHD | 0 |
Register 234h | 0 | 0 | DIS DITH CHD | 0 | DIS DITH CHD | 0 | 0 | 0 |
Register 239h | 0 | 0 | 0 | 0 | SP1 CHD | 0 | 0 | 0 |
Register 308 | HIGH IF MODE <5:4> | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 41Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE2 | 0 |
Register 422h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHB | 0 |
Register 434h | 0 | 0 | DIS DITH CHB | 0 | DIS DITH CHB | 0 | 0 | 0 |
Register 439h | 0 | 0 | 0 | 0 | SP1 CHB | 0 | 0 | 0 |
Register 51Dh | 0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE3 | 0 |
Register 522h | 0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHC | 0 |
Register 534h | 0 | 0 | DIS DITH CHC | 0 | DIS DITH CHC | 0 | 0 | 0 |
Register 539h | 0 | 0 | 0 | 0 | SP1 CHC | 0 | 0 | 0 |
Register 608h | HIGH IF MODE <7:6> | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 70Ah | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PDN SYSREF |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS DITH CHA | DIS DITH CHB | DIS DITH CHC | DIS DITH CHD | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | DIS DITH CHA | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 134h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
5-4 | DIS DITH CHB | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 434h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
3-2 | DIS DITH CHC | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 534h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
1-0 | DIS DITH CHD | R/W | 0h | These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 234h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | ODD EVEN |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
0 | ODD EVEN | R/W | 0h | This bit selects the bit sequence on the output wires (in 2-wire mode only). 0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and so forth appear on wire-1. 1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and so forth appear on wire-1. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | FLIP WIRE |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | FLIP WIRE | R/W | 0h | This bit flips the data on the output wires. Valid only in two wire configuration. 0 = Default 1 = Data on output wires is flipped. Pin D0x becomes D1x, and vice versa. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1W-2W |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | 1W-2W | R/W | 0h | This bit transmits output data on either one or two wires. 0 = Output data are transmitted on two wires (Dx0P, Dx0M and Dx1P, Dx1M) 1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this mode, the recommended fS is less than 80 MSPS. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | TEST PATTERN EN | R/W | 0h | This bit enables test pattern selection for the digital outputs. 0 = Normal output 1 = Test pattern output enabled |
0 | RESET | R/W | 0h | This bit applies a software reset. This bit resets all internal registers to the default values and self-clears to 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | OVR ON LSB |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | OVR ON LSB | R/W | 0h | This bit provides OVR information on the LSB bits. 0 = Output data bit 0 functions as the LSB of the 12-bit data 1 = Output data bit 0 carries the overrange (OVR) information |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | ALIGN TEST PATTERN | DATA FORMAT |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | ALIGN TEST PATTERN | R/W | 0h | This bit aligns the test patterns across the outputs of both channels. 0 = Test patterns of both channels are free running 1 = Test patterns of both channels are aligned |
0 | DATA FORMAT | R/W | 0h | This bit selects th digital output data format. 0 = Twos complement 1 = Offset binary |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA TEST PATTERN | CHB TEST PATTERN | ||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CHA TEST PATTERN | R/W | 0h | These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, and 599 Others = Do not use |
3-0 | CHB TEST PATTERN | R/W | 0h | These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, and 599 Others = Do not use |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHC TEST PATTERN | CHD TEST PATTERN | ||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CHC TEST PATTERN | R/W | 0h | These bits control the test pattern for channel C after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0110 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 1000 = Deskew pattern: data are AAAh. 1010 = PRBS pattern: data are a sequence of pseudo random numbers. 1011 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use |
3-0 | CHD TEST PATTERN | R/W | 0h | These bits control the test pattern for channel D after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0110 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 1000 = Deskew pattern: data are AAAh. 1010 = PRBS pattern: data are a sequence of pseudo random numbers. 1011 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN[11:4] | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CUSTOM PATTERN[11:4] | R/W | 0h | These bits set the 12-bit custom pattern (bits 11-4) for all channels. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM PATTERN[3:0] | 0 | 0 | 0 | 0 | |||
R/W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | CUSTOM PATTERN[3:0] | R/W | 0h | These bits set the 12-bit custom pattern (bits 3-0) for all channels. |
3-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | LOW SPEED ENABLE | |
W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1-0 | LOW SPEED ENABLE | R/W | 0h | Enables low speed operation in 1-wire and 2-wire mode. Depending upon sampling frequency, write this bit as per Table 21. |
fS, MSPS | REGISTER BIT LOW SPEED ENABLE | |||
---|---|---|---|---|
MIN | MAX | 1-WIRE MODE | 2-WIRE MODE | |
25 | 125 | 00 | 00 | |
20 | 25 | 10 | 11 | |
15 | 20 | 10 | Not supported |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHA PDN | CHB PDN | CHC PDN | CHD PDN | STANDBY | GLOBAL PDN | 0 | CONFIG PDN PIN |
W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CHA PDN | W | 0h | 0 = Normal operation 1 = Power-down channel A |
6 | CHB PDN | R/W | 0h | 0 = Normal operation 1 = Power-down channel B |
5 | CHC PDN | R/W | 0h | 0 = Normal operation 1 = Power-down channel C |
4 | CHD PDN | W | 0h | 0 = Normal operation 1 = Power-down channel D |
3 | STANDBY | R/W | 0h | The ADCs of both channels enter standby. 0 = Normal operation 1 = Standby |
2 | GLOBAL PDN | R/W | 0h | 0 = Normal operation 1 = Global power-down |
1 | 0 | W | 0h | Must write 0. |
0 | CONFIG PDN PIN | R/W | 0h | This bit configures the PDN pin as either a global power-down or standby pin. 0 = Logic high voltage on the PDN pin sends the device into global power-down 1 = Logic high voltage on the PDN pin sends the device into standby |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LVDS SWING | |||||||
R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LVDS SWING | R/W | 0h | These bits control the swing of the LVDS outputs (including the data output, bit clock, and frame clock). |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CLK DIV | R/W | 0h | These bits select the internal clock divider for the input sampling clock. 00 = Divide-by-1 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE0 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE0 | Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. |
||
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHA | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHA | R/W | 0h | This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHA | 0 | DIS DITH CHA | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHA | R/W | 0h | Set this bit along with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHA | R/W | 0h | Set this bit along with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHA | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHA | R/W | 0h | This bit sets the special mode for best performance on channel A. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE1 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE1 | R/W | 0h | Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHD | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHD | R/W | 0h | This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHD | 0 | DIS DITH CHD | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHD | R/W | 0h | Set this bit with bits 1 and 0 of register 01h. 00 = Default 11 = Dither is disabled for channel D. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHD | R/W | 0h | Set this bit with bits 1 and 0 of register 01h. 00 = Default 11 = Dither is disabled for channel D. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHD | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHD | R/W | 0h | This bit sets the special mode for best performance on channel D. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HIGH IF MODE<5:4> | 0 | 0 | 0 | 0 | 0 | 0 | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HIGH IF MODE<5:4> | R/W | 0h | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE2 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE2 | R/W | 0h | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHB | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHB | R/W | 0h | This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHB | 0 | DIS DITH CHB | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHB | R/W | 0h | Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHB | R/W | 0h | Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHB | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHB | R/W | 0h | This bit sets the special mode for best performance on channel B. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | HIGH IF MODE3 | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | HIGH IF MODE3 | R/W | 0h | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | DIS CHOP CHC | 0 |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0. |
1 | DIS CHOP CHC | R/W | 0h | This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc |
0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | DIS DITH CHC | 0 | DIS DITH CHC | 0 | 0 | 0 |
W-0h | W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | 0 | W | 0h | Must write 0. |
5 | DIS DITH CHC | R/W | 0h | Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
4 | 0 | W | 0h | Must write 0. |
3 | DIS DITH CHC | R/W | 0h | Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.2 dB at 70 MHz. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SP1 CHC | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0. |
3 | SP1 CHC | R/W | 0h | This bit sets the special mode for best performance on channel C. Always write 1 after reset. |
2-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HIGH IF MODE<7:6> | 0 | 0 | 0 | 0 | 0 | 0 | |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HIGH IF MODE<7:6> | R/W | 0h | Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. |
5-0 | 0 | W | 0h | Must write 0. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | PDN SYSREF |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | 0 | W | 0h | Must write 0. |
0 | PDN SYSREF | R/W | 0h | If the SYSREF pins are not used in the system, the SYSREF buffer must be powered down by setting this bit. 0 = Normal operation 1 = Powers down the SYSREF buffer |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 181 and Figure 182 show the impedance (Zin = Rin || Cin) across the ADC input pins.
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.
A typical application involving using two back-to-back coupled transformers is illustrated in Figure 183. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches.
Figure 184 shows the performance obtained by using the circuit shown in Figure 183.
SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc |
See the Design Requirements section for further details.
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 185.
Figure 186 shows the performance obtained by using the circuit shown in Figure 185.
SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS, THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc |
See the Design Requirements section for further details.
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 187.
Figure 188 shows the performance obtained by using the circuit shown in Figure 187.
SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS, THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc |
The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply requirements during device power-up. AVDD and DVDD can power up in any order.