The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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ADC342x | VQFN (56) | 8.00 mm × 8.00 mm |
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PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 6, 7, 10, 11, 14, 15, 20, 23, 28, 29, 32, 33, 36 | I | Analog 1.8-V power supply |
CLKM | 21 | I | Negative differential clock input for the ADC |
CLKP | 22 | I | Positive differential clock input for the ADC |
DA0M | 4 | O | Negative serial LVDS output for wire-0 of channel A |
DA0P | 3 | O | Positive serial LVDS output for wire-0 of channel A |
DA1M | 2 | O | Negative serial LVDS output for wire-1 of channel A |
DA1P | 1 | O | Positive serial LVDS output for wire-1 of channel A |
DB0M | 56 | O | Negative serial LVDS output for wire-0 of channel B |
DB0P | 55 | O | Positive serial LVDS output for wire-0 of channel B |
DB1M | 54 | O | Negative serial LVDS output for wire-1 of channel B |
DB1P | 53 | O | Positive serial LVDS output for wire-1 of channel B |
DC0M | 46 | O | Negative serial LVDS output for wire-0 of channel C |
DC0P | 45 | O | Positive serial LVDS output for wire-0 of channel C |
DC1M | 44 | O | Negative serial LVDS output for wire-1 of channel C |
DC1P | 43 | O | Positive serial LVDS output for wire-1 of channel C |
DD0M | 42 | O | Negative serial LVDS output for wire-0 of channel D |
DD0P | 41 | O | Positive serial LVDS output for wire-0 of channel D |
DD1M | 40 | O | Negative serial LVDS output for wire-1 of channel D |
DD1P | 39 | O | Positive serial LVDS output for wire-1 of channel D |
DCLKM | 51 | O | Negative bit clock output |
DCLKP | 50 | O | Positive bit clock output |
DVDD | 5, 38, 47, 52 | I | Digital 1.8-V power supply |
FCLKM | 49 | O | Negative frame clock output |
FCLKP | 48 | O | Positive frame clock output |
GND | PowerPAD™ | I | Ground, 0 V |
INAM | 8 | I | Negative differential analog input for channel A |
INAP | 9 | I | Positive differential analog input for channel A |
INBM | 13 | I | Negative differential analog input for channel B |
INBP | 12 | I | Positive differential analog input for channel B |
INCM | 30 | I | Negative differential analog input for channel C |
INCP | 31 | I | Positive differential analog input for channel C |
INDM | 35 | I | Negative differential analog input for channel D |
INDP | 34 | I | Positive differential analog input for channel D |
PDN | 37 | I | Power-down control. This pin can be configured via the SPI. This pin has an internal 150-kΩ pulldown resistor. |
RESET | 24 | I | Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. |
SCLK | 16 | I | Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. |
SDATA | 17 | I | Serial interface data input. This pin has an internal 150-kΩ pulldown resistor. |
SDOUT | 19 | O | Serial interface data output |
SEN | 18 | I | Serial interface enable; active low. This pin has an internal 150-kΩ pullup resistor to AVDD. |
SYSREFM | 26 | I | Negative external SYSREF input |
SYSREFP | 25 | I | Positive external SYSREF input |
VCM | 27 | O | Common-mode voltage for analog inputs |