SBAS673A July   2014  – October 2015 ADC3421 , ADC3422 , ADC3423 , ADC3424

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADC3421, ADC3422
    7. 7.7  Electrical Characteristics: ADC3423, ADC3424
    8. 7.8  AC Performance: ADC3421
    9. 7.9  AC Performance: ADC3422
    10. 7.10 AC Performance: ADC3423
    11. 7.11 AC Performance: ADC3424
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3421
    16. 7.16 Typical Characteristics: ADC3422
    17. 7.17 Typical Characteristics: ADC3423
    18. 7.18 Typical Characteristics: ADC3424
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 12x Serialization
        2. 9.3.3.2 Two-Wire Interface: 6x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
      4. 9.4.4 Internal Dither Algorithm
      5. 9.4.5 Summary of Performance Mode Registers
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Serial Register Description
        1. 9.6.1.1 Register 13h (address = 13h)
        2. 9.6.1.2 Register 11Dh (address = 11Dh)
        3. 9.6.1.3 Register 21Dh (address = 21Dh)
        4. 9.6.1.4 Register 308h (address = 308h)
        5. 9.6.1.5 Register 41Dh (address = 41Dh)
        6. 9.6.1.6 Register 51Dh (address = 51Dh)
        7. 9.6.1.7 Register 608h (address = 608h)
        8. 9.6.1.8 Register 70Ah (address = 70Ah)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

8.1 Timing Diagrams

ADC3421 ADC3422 ADC3423 ADC3424 tim_lvds_vo_level_bas550.gif
1. With an external 100-Ω termination.
Figure 129. Serial LVDS Output Voltage Levels
ADC3421 ADC3422 ADC3423 ADC3424 opt_tmng_dgrm_sbas673.gif Figure 130. Output Timing Diagram
ADC3421 ADC3422 ADC3423 ADC3424 Stp_hld_tmng_BAS671.gif Figure 131. Setup and Hold Time