SBAS673A July   2014  – October 2015 ADC3421 , ADC3422 , ADC3423 , ADC3424

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADC3421, ADC3422
    7. 7.7  Electrical Characteristics: ADC3423, ADC3424
    8. 7.8  AC Performance: ADC3421
    9. 7.9  AC Performance: ADC3422
    10. 7.10 AC Performance: ADC3423
    11. 7.11 AC Performance: ADC3424
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3421
    16. 7.16 Typical Characteristics: ADC3422
    17. 7.17 Typical Characteristics: ADC3423
    18. 7.18 Typical Characteristics: ADC3424
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 12x Serialization
        2. 9.3.3.2 Two-Wire Interface: 6x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
      4. 9.4.4 Internal Dither Algorithm
      5. 9.4.5 Summary of Performance Mode Registers
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Serial Register Description
        1. 9.6.1.1 Register 13h (address = 13h)
        2. 9.6.1.2 Register 11Dh (address = 11Dh)
        3. 9.6.1.3 Register 21Dh (address = 21Dh)
        4. 9.6.1.4 Register 308h (address = 308h)
        5. 9.6.1.5 Register 41Dh (address = 41Dh)
        6. 9.6.1.6 Register 51Dh (address = 51Dh)
        7. 9.6.1.7 Register 608h (address = 608h)
        8. 9.6.1.8 Register 70Ah (address = 70Ah)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 181 and Figure 182 show the impedance (Zin = Rin || Cin) across the ADC input pins.

ADC3421 ADC3422 ADC3423 ADC3424 D024_BAS671.gif Figure 181. Differential Input Resistance, RIN
ADC3421 ADC3422 ADC3423 ADC3424 D025_BAS671.gif Figure 182. Differential Input Capacitance, CIN

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

ADC3421 ADC3422 ADC3423 ADC3424 Drv_Crct_Lw_Inpt_Freq_BAS663.gif Figure 183. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is illustrated in Figure 183. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curve

Figure 184 shows the performance obtained by using the circuit shown in Figure 183.

ADC3421 ADC3422 ADC3423 ADC3424 D201_SBAS673.gif
SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS,
THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc
Figure 184. Performance FFT at 10 MHz (Low Input Frequency)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

ADC3421 ADC3422 ADC3423 ADC3424 Drv_Crct_Md_Inpt_Freq_BAS663.gif Figure 185. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 185.

10.2.2.3 Application Curve

Figure 186 shows the performance obtained by using the circuit shown in Figure 185.

ADC3421 ADC3422 ADC3423 ADC3424 D205_SBAS673.gif
SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS,
THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc
Figure 186. Performance FFT at 170 MHz (Mid Input Frequency)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

ADC3421 ADC3422 ADC3423 ADC3424 Drv_Crct_Hg_Inpt_Freq_BAS663.gif Figure 187. Driving Circuit for High Input Frequencies (fIN > 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 187.

10.2.3.3 Application Curve

Figure 188 shows the performance obtained by using the circuit shown in Figure 187.

ADC3421 ADC3422 ADC3423 ADC3424 D209_SBAS673.gif
SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS,
THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc
Figure 188. Performance FFT at 450 MHz (High Input Frequency)