SBAS673A July   2014  – October 2015 ADC3421 , ADC3422 , ADC3423 , ADC3424

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADC3421, ADC3422
    7. 7.7  Electrical Characteristics: ADC3423, ADC3424
    8. 7.8  AC Performance: ADC3421
    9. 7.9  AC Performance: ADC3422
    10. 7.10 AC Performance: ADC3423
    11. 7.11 AC Performance: ADC3424
    12. 7.12 Digital Characteristics
    13. 7.13 Timing Requirements: General
    14. 7.14 Timing Requirements: LVDS Output
    15. 7.15 Typical Characteristics: ADC3421
    16. 7.16 Typical Characteristics: ADC3422
    17. 7.17 Typical Characteristics: ADC3423
    18. 7.18 Typical Characteristics: ADC3424
    19. 7.19 Typical Characteristics: Common
    20. 7.20 Typical Characteristics: Contour
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
      3. 9.3.3 Digital Output Interface
        1. 9.3.3.1 One-Wire Interface: 12x Serialization
        2. 9.3.3.2 Two-Wire Interface: 6x Serialization
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Divider
      2. 9.4.2 Chopper Functionality
      3. 9.4.3 Power-Down Control
      4. 9.4.4 Internal Dither Algorithm
      5. 9.4.5 Summary of Performance Mode Registers
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
    6. 9.6 Register Maps
      1. 9.6.1 Serial Register Description
        1. 9.6.1.1 Register 13h (address = 13h)
        2. 9.6.1.2 Register 11Dh (address = 11Dh)
        3. 9.6.1.3 Register 21Dh (address = 21Dh)
        4. 9.6.1.4 Register 308h (address = 308h)
        5. 9.6.1.5 Register 41Dh (address = 41Dh)
        6. 9.6.1.6 Register 51Dh (address = 51Dh)
        7. 9.6.1.7 Register 608h (address = 608h)
        8. 9.6.1.8 Register 70Ah (address = 70Ah)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Analog supply voltage range, AVDD –0.3 2.1 V
Digital supply voltage range, DVDD –0.3 2.1 V
Voltage applied to
input pins		 INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 min (1.9, AVDD + 0.3) V
CLKP, CLKM –0.3 AVDD + 0.3
SYSREFP, SYSREFM –0.3 AVDD + 0.3
SCLK, SEN, SDATA, RESET, PDN –0.3 3.9
Temperature Operating free-air, TA –40 85 ºC
Operating junction, TJ 125
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(3)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage range 1.7 1.8 1.9 V
DVDD Digital supply voltage range 1.7 1.8 1.9 V
ANALOG INPUT
VID Differential input voltage For input frequencies < 450 MHz 2 VPP
For input frequencies < 600 MHz 1
VIC Input common-mode voltage VCM ± 0.025 V
CLOCK INPUT
Input clock frequency Sampling clock frequency 15(2) 125(1) MSPS
Input clock amplitude (differential) Sine wave, ac-coupled 0.2 1.5 VPP
LPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
Input clock duty cycle 35% 50% 65%
Input clock common-mode voltage 0.95 V
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF
RLOAD Single-ended load resistance 100 Ω
(1) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.
(2) See Table 3 for details.
(3) After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details.

7.4 Thermal Information

THERMAL METRIC(1) ADC342x UNIT
RTQ (VQFN)
56 PINS
RθJA Junction-to-ambient thermal resistance 25.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W
RθJB Junction-to-board thermal resistance 3.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: General

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Differential input full-scale 2.0 VPP
ri Input resistance Differential at dc 6.6 kΩ
ci Input capacitance Differential at dc 3.7 pF
VOC(VCM) VCM common-mode voltage output 0.95 V
VCM output current capability 10 mA
Input common-mode current Per analog input pin 1.5 µA/MSPS
Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz
DC ACCURACY
EO Offset error –25 25 mV
αEO Temperature coefficient of offset error ± 0.024 mV/°C
EG(REF) Gain error as a result of internal reference inaccuracy alone –2 2 %FS
EG(CHAN) Gain error of channel alone –2 %FS
α(EGCHAN) Temperature coefficient of EG(CHAN) ±0.008 Δ%FS/Ch
CHANNEL-TO-CHANNEL ISOLATION
Crosstalk(1) fIN = 10 MHz Near channel 105 dB
Far channel 105
fIN = 100 MHz Near channel 95
Far channel 105
fIN = 200 MHz Near channel 94
Far channel 105
fIN = 230 MHz Near channel 92
Far channel 105
fIN = 300 MHz Near channel 85
Far channel 105
(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.

7.6 Electrical Characteristics: ADC3421, ADC3422

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC3421 ADC3422 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 25 50 MSPS
Resolution 12 12 Bits
1.8-V analog supply current 54 71 71 90 mA
1.8-V digital supply current 45 71 56 90 mA
Total power dissipation 177 240 228 305 mW
Global power-down dissipation 5 17 5 17 mW
Standby power-down dissipation 34 75 35 75 mW

7.7 Electrical Characteristics: ADC3423, ADC3424

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER ADC3423 ADC3424 UNIT
MIN TYP MAX MIN TYP MAX
ADC clock frequency 80 125 MSPS
Resolution 12 12 Bits
1.8-V analog supply current 92 107 119 145 mA
1.8-V digital supply current 68 100 98 145 mA
Total power dissipation 288 365 391 475 mW
Global power-down dissipation 5 17 5 17 mW
Standby power-down dissipation 40 88 43 103 mW

7.8 AC Performance: ADC3421

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3421 (fS = 25 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 70.9 71.1 dBFS
fIN = 20 MHz 68.9 70.7 70.9
fIN = 70 MHz 70.4 70.6
fIN = 100 MHz 70.3 70.5
fIN = 170 MHz 69.7 69.9
fIN = 230 MHz 68.9 69.1
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 70.2 70.5 dBFS
fIN = 20 MHz 70.1 70.3
fIN = 70 MHz 69.8 70.0
fIN = 100 MHz 69.6 69.8
fIN = 170 MHz 69.2 69.3
fIN = 230 MHz 68.3 68.5
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –141.5 –141.7 dBFS/Hz
fIN = 20 MHz –141.3 –139.5 –141.5
fIN = 70 MHz –141.0 –141.2
fIN = 100 MHz –140.9 –141.1
fIN = 170 MHz –140.3 –140.5
fIN = 230 MHz –139.5 –139.7
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 71 71.1 dBFS
fIN = 20 MHz 67.9 70.8 70.9
fIN = 70 MHz 69.5 70
fIN = 100 MHz 70.5 70.7
fIN = 170 MHz 69.6 69.8
fIN = 230 MHz 68.7 68.7
ENOB(1) Effective number of bits fIN = 10 MHz 11.5 11.5 Bits
fIN = 20 MHz 11 11.4 11.4
fIN = 70 MHz 11.4 11.4
fIN = 100 MHz 11.4 11.4
fIN = 170 MHz 11.3 11.3
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 93 90 dBc
fIN = 20 MHz 84 91 85
fIN = 70 MHz 93 88
fIN = 100 MHz 85 82
fIN = 170 MHz 86 85
fIN = 230 MHz 82 82
HD2 Second-order harmonic distortion fIN = 10 MHz 93 92 dBc
fIN = 20 MHz 84 100 94
fIN = 70 MHz 93 92
fIN = 100 MHz 94 93
fIN = 170 MHz 86 85
fIN = 230 MHz 86 82
HD3 Third-order harmonic distortion fIN = 10 MHz 96 90 dBc
fIN = 20 MHz 84 91 85
fIN = 70 MHz 93 88
fIN = 100 MHz 85 82
fIN = 170 MHz 89 89
fIN = 230 MHz 82 82
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 92 dBc
fIN = 20 MHz 87 98 91
fIN = 70 MHz 96 92
fIN = 100 MHz 95 93
fIN = 170 MHz 92 90
fIN = 230 MHz 97 91
THD Total harmonic distortion fIN = 10 MHz 90 86 dBc
fIN = 20 MHz 81 90 83
fIN = 70 MHz 89 85
fIN = 100 MHz 84 80
fIN = 170 MHz 84 83
fIN = 230 MHz 80 79
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –98 –98 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –91 –91
(1) Reported from a 1-MHz offset.

7.9 AC Performance: ADC3422

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3422 (fS = 50 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 70.8 71 dBFS
fIN = 20 MHz 68.9 70.6 70.8
fIN = 70 MHz 70.5 70.7
fIN = 100 MHz 70.4 70.6
fIN = 170 MHz 69.8 70.1
fIN = 230 MHz 68.8 69
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 70.2 70.4
fIN = 20 MHz 69.8 70.0
fIN = 70 MHz 69.7 69.9
fIN = 100 MHz 69.8 70.1
fIN = 170 MHz 69.3 69.5
fIN = 230 MHz 68.2 68.4
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –144.6 –144.8 dBFS/Hz
fIN = 20 MHz –144.4 –142.7 –144.6
fIN = 70 MHz –144.3 –144.5
fIN = 100 MHz –144.2 –144.4
fIN = 170 MHz –143.6 –143.9
fIN = 230 MHz –142.6 –142.8
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.8 71 dBFS
fIN = 20 MHz 67.9 70.7 70.9
fIN = 70 MHz 70.3 70.6
fIN = 100 MHz 70.6 70.8
fIN = 170 MHz 69.7 69.9
fIN = 230 MHz 68.6 68.8
ENOB(1) Effective number of bits fIN = 10 MHz 11.5 11.5 Bits
fIN = 20 MHz 11 11.4 11.5
fIN = 70 MHz 11.4 11.5
fIN = 100 MHz 11.4 11.5
fIN = 170 MHz 11.3 11.3
fIN = 230 MHz 11.1 11.1
SFDR Spurious-free dynamic range fIN = 10 MHz 90 92 dBc
fIN = 20 MHz 82 95 90
fIN = 70 MHz 93 92
fIN = 100 MHz 87 87
fIN = 170 MHz 87 86
fIN = 230 MHz 83 83
HD2 Second-order harmonic distortion fIN = 10 MHz 95 92 dBc
fIN = 20 MHz 83 98 95
fIN = 70 MHz 93 92
fIN = 100 MHz 94 92
fIN = 170 MHz 87 86
fIN = 230 MHz 85 83
HD3 Third-order harmonic distortion fIN = 10 MHz 90 92 dBc
fIN = 20 MHz 82 94 92
fIN = 70 MHz 94 92
fIN = 100 MHz 87 87
fIN = 170 MHz 88 89
fIN = 230 MHz 83 88
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 93 dBc
fIN = 20 MHz 87 99 93
fIN = 70 MHz 98 92
fIN = 100 MHz 95 94
fIN = 170 MHz 96 89
fIN = 230 MHz 96 90
THD Total harmonic distortion fIN = 10 MHz 88 87 dBc
fIN = 20 MHz 79 89 89
fIN = 70 MHz 90 87
fIN = 100 MHz 86 85
fIN = 170 MHz 84 83
fIN = 230 MHz 81 81
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –95 –95 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –88 –88
(1) Reported from a 1-MHz offset.

7.10 AC Performance: ADC3423

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3423 (fS = 80 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 70.7 70.9 dBFS
fIN = 70 MHz 68.7 70.5 70.7
fIN = 100 MHz 70.3 70.5
fIN = 170 MHz 70.1 70.3
fIN = 230 MHz 69.6 69.9
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 70.3 70.5
fIN = 70 MHz 70.1 70.4
fIN = 100 MHz 69.9 70.2
fIN = 170 MHz 69.7 69.9
fIN = 230 MHz 69.3 69.6
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –146.6 –146.8 dBFS/Hz
fIN = 70 MHz –146.4 –144.6 –146.6
fIN = 100 MHz –146.2 –146.4
fIN = 170 MHz –146.0 –146.2
fIN = 230 MHz –145.5 –145.8
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.7 70.8 dBFS
fIN = 70 MHz 67.7 70.3 70.4
fIN = 100 MHz 70.4 70.7
fIN = 170 MHz 70 70.2
fIN = 230 MHz 69.5 69.7
ENOB(1) Effective number of bits fIN = 10 MHz 11.5 11.5 Bits
fIN = 70 MHz 11 11.4 11.4
fIN = 100 MHz 11.4 11.5
fIN = 170 MHz 11.3 11.4
fIN = 230 MHz 11.3 11.3
SFDR Spurious-free dynamic range fIN = 10 MHz 90 90 dBc
fIN = 70 MHz 81 91 90
fIN = 100 MHz 93 93
fIN = 170 MHz 88 86
fIN = 230 MHz 87 85
HD2 Second-order harmonic distortion fIN = 10 MHz 94 91 dBc
fIN = 70 MHz 81 96 92
fIN = 100 MHz 97 93
fIN = 170 MHz 88 86
fIN = 230 MHz 87 85
HD3 Third-order harmonic distortion fIN = 10 MHz 90 90 dBc
fIN = 70 MHz 81 91 90
fIN = 100 MHz 93 99
fIN = 170 MHz 96 93
fIN = 230 MHz 87 87
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 99 94 dBc
fIN = 70 MHz 86 98 93
fIN = 100 MHz 94 94
fIN = 170 MHz 95 92
fIN = 230 MHz 94 91
THD Total harmonic distortion fIN = 10 MHz 88 86 dBc
fIN = 70 MHz 78 89 86
fIN = 100 MHz 91 90
fIN = 170 MHz 87 84
fIN = 230 MHz 84 82
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 –97 –97 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 –92 –92
(1) Reported from a 1-MHz offset.

7.11 AC Performance: ADC3424

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS ADC3424 (fS = 125 MSPS) UNIT
DITHER ON DITHER OFF
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio
(from 1-MHz offset)		 fIN = 10 MHz 70.5 70.7 dBFS
fIN = 70 MHz 68 70.3 70.6
fIN = 100 MHz 70.1 70.4
fIN = 170 MHz 69.8 70.3
fIN = 230 MHz 69.2 69.9
Signal-to-noise ratio
(full Nyquist band)		 fIN = 10 MHz 70.3 70.5
fIN = 70 MHz 70.1 70.4
fIN = 100 MHz 70.0 70.2
fIN = 170 MHz 69.6 70.1
fIN = 230 MHz 69.0 69.7
NSD(1) Noise spectral density (averaged across Nyquist zone) fIN = 10 MHz –148.4 –148.6 dBFS/Hz
fIN = 70 MHz –148.2 –145.9 –148.5
fIN = 100 MHz –148.0 –148.3
fIN = 170 MHz –147.7 –148.2
fIN = 230 MHz –147.1 –147.8
SINAD(1) Signal-to-noise and distortion ratio fIN = 10 MHz 70.5 70.6 dBFS
fIN = 70 MHz 67 70.3 70.5
fIN = 100 MHz 70.1 70.5
fIN = 170 MHz 69.7 70.1
fIN = 230 MHz 68.6 69.1
ENOB(1) Effective number of bits fIN = 10 MHz 11.4 11.4 Bits
fIN = 70 MHz 10.8 11.4 11.4
fIN = 100 MHz 11.4 11.4
fIN = 170 MHz 11.3 11.4
fIN = 230 MHz 11.2 11.3
SFDR Spurious-free dynamic range fIN = 10 MHz 93 89 dBc
fIN = 70 MHz 80 94 90
fIN = 100 MHz 90 87
fIN = 170 MHz 86 85
fIN = 230 MHz 81 80
HD2 Second-order harmonic distortion fIN = 10 MHz 93 92 dBc
fIN = 70 MHz 80 94 91
fIN = 100 MHz 90 91
fIN = 170 MHz 86 85
fIN = 230 MHz 81 80
HD3 Third-order harmonic distortion fIN = 10 MHz 96 88 dBc
fIN = 70 MHz 81 95 89
fIN = 100 MHz 97 90
fIN = 170 MHz 93 87
fIN = 230 MHz 87 86
Non
HD2, HD3		 Spurious-free dynamic range (excluding HD2, HD3) fIN = 10 MHz 100 93 dBc
fIN = 70 MHz 86 99 94
fIN = 100 MHz 94 93
fIN = 170 MHz 95 92
fIN = 230 MHz 94 90
THD Total harmonic distortion fIN = 10 MHz 90 85 dBc
fIN = 70 MHz 77 90 85
fIN = 100 MHz 88 86
fIN = 170 MHz 85 82
fIN = 230 MHz 80 78
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 45 MHz,
fIN2 = 50 MHz		 95 95 dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz		 89 89
(1) Reported from a 1-MHz offset.

7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V
VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 0.4 V
IIH High-level input current RESET, SDATA, SCLK, PDN VHIGH = 1.8 V 10 µA
SEN(1) VHIGH = 1.8 V 0 µA
IIL Low-level input current RESET, SDATA, SCLK, PDN VLOW = 0 V 0 µA
SEN VLOW = 0 V 10 µA
DIGITAL INPUTS (SYSREFP, SYSREFM)
VIH High-level input voltage 1.3 V
VIL Low-level input voltage 0.5 V
Common-mode voltage for SYSREF 0.9 V
DIGITAL OUTPUTS (CMOS Interface, SDOUT)
VOH High-level output voltage DVDD – 0.1 DVDD V
VOL Low-level output voltage 0 0.1 V
DIGITAL OUTPUTS (LVDS Interface)
VODH High-level output differential voltage With an external 100-Ω termination 280 350 460 mV
VODL Low-level output differential voltage With an external 100-Ω termination –460 –350 –280 mV
VOCM Output common-mode voltage 1.05 V
(1) SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8 V or 3.3 V CMOS buffers.

7.13 Timing Requirements: General

Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C.
MIN TYP MAX UNIT
tA Aperture delay 1.24 1.44 1.64 ns
Aperture delay matching between two channels of the same device ±70 ps
Aperture delay variation between two devices at same temperature and supply voltage ±150 ps
tJ Aperture jitter 130 fS rms
Wake-up time: Time to valid data after exiting standby power-down mode 35 200 µs
Time to valid data after exiting global power-down mode
(in this mode, both channels power down)		 85 450 µs
ADC latency(6): 2-wire mode (default) 9 Clock cycles
1-wire mode 8 Clock cycles
tSU_SYSREF SYSREF reference time: Setup time for SYSREF referenced to input clock rising edge 1000 ps
tH_SYSREF Hold time for SYSREF referenced to input clock rising edge 100 ps

7.14 Timing Requirements: LVDS Output(4)(1)

Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x Serialization (2-Wire Mode), CLOAD = 3.3 pF(2), and RLOAD = 100 Ω(3), unless otherwise noted.. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C.
MIN TYP MAX UNIT
tSU Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM)(5) 0.43 0.5 ns
tHO Data hold time: zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid(5)		 0.48 0.58 ns
tPDI Clock propagation delay: input clock falling edge cross-over to frame clock rising edge cross-over
(15 MSPS < sampling frequency < 125 MSPS)		 1-wire mode 2.7 4.5 6.5 ns
2-wire mode 0.44 × tS + tDELAY ns
tDELAY Delay time 3 4.5 5.9 ns
LVDS bit clock duty cycle: duty cycle of differential clock
(CLKOUTP – CLKOUTM)		 49%
tFALL,
tRISE		 Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
15 MSPS ≤ Sampling frequency ≤ 125 MSPS		 0.11 ns
tCLKRISE,
tCLKFALL		 Output clock rise time, output clock fall time: rise time measured from
–100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS		 0.11 ns
(1) Timing parameters are ensured by design and characterization and are not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.
(6) Overall latency = ADC latency + tPDI.

Table 1. LVDS Timing at Lower Sampling Frequencies: 6X Serialization (2-Wire Mode)

SAMPLING FREQUENCY
(MSPS)		 SETUP TIME
(tSU, ns)		 HOLD TIME
(tHO, ns)
MIN TYP MAX MIN TYP MAX
25 2.61 3.06 2.75 3.12
40 1.69 1.9 1.8 1.98
60 1.11 1.23 1.18 1.31
80 0.81 0.89 0.88 0.97
100 0.6 0.68 0.68 0.77

Table 2. LVDS Timings at Lower Sampling Frequencies: 12X Serialization (1-Wire Mode)

SAMPLING FREQUENCY
(MSPS)		 SETUP TIME
(tSU, ns)		 HOLD TIME
(tHO, ns)
MIN TYP MAX MIN TYP MAX
25 1.3 1.48 1.32 1.57
40 0.76 0.88 0.79 0.97
50 0.57 0.68 0.61 0.77
60 0.42 0.55 0.45 0.62
70 0.35 0.44 0.4 0.51
80 0.26 0.35 0.35 0.43

7.15 Typical Characteristics: ADC3421

Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3421 ADC3422 ADC3423 ADC3424 D801_SBAS673.gif
SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS,
THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D803_SBAS673.gif
SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.3 dBFS,
THD = 91 dBc, HD2 = 105 dBc, HD3 = 92 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D805_SBAS673.gif
SFDR = 87 dBc, SNR = 69.8 dBFS, SINAD = 69.7 dBFS,
THD = 85 dBc, HD2 = 90 dBc, HD3 = 87 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D807_SBAS673.gif
SFDR = 77 dBc, SNR = 68.2 dBFS, SINAD = 67.7 dBFS,
THD = 75 dBc, HD2 = 77 dBc, HD3 = 83 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D809_SBAS673.gif
SFDR = 67 dBc, SNR = 66.4 dBFS, SINAD = 66.4 dBFS,
THD = 93 dBc, HD2 = 67 dBc, HD3 = 88 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D811_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90,
each tone at = –7 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D813_SBAS673.gif
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 91,
each tone at = –7 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D815_SBAS673.gif
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D817_SBAS673.gif
Figure 17. Signal-to-Noise Ratio vs Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D819_SBAS673.gif
Figure 19. Performance vs Input Amplitude (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D821_SBAS673.gif
Figure 21. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D823_SBAS673.gif
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D825_SBAS673.gif
Figure 25. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D827_SBAS673.gif
Figure 27. Performance vs Clock Amplitude (40 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D829_SBAS673.gif
Figure 29. Performance vs Clock Duty Cycle (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D802_SBAS673.gif
SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS,
THD = 89 dBc, HD2 = 90 dBc, HD3 = 106 dBc
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D804_SBAS673.gif
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 88 dBc, HD2 = 91 dBc, HD3 = 101 dBc
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D806_SBAS673.gif
SFDR = 85 dBc, SNR = 70 dBFS, SINAD = 69.8 dBFS,
THD = 86 dBc, HD2 = 85 dBc, HD3 = 92 dBc
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D808_SBAS673.gif
SFDR = 75 dBc, SNR = 68.4 dBFS, SINAD = 67.5 dBFS,
THD = 74 dBc, HD2 = 75 dBc, HD3 = 80 dBc
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D810_SBAS673.gif
SFDR = 66 dBc, SNR = 66.5 dBFS, SINAD = 66.5 dBFS,
THD = 87 dBc, HD2 = 66 dBc, HD3 = 93 dBc
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D812_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105,
each tone at = –36 dBFS
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D814_SBAS673.gif
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 98 dBFS,
each tone at –36 dBFS
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D816_SBAS673.gif
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D818_SBAS673.gif
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D820_SBAS673.gif
Figure 20. Performance vs Input Amplitude (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D822_SBAS673.gif
Figure 22. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D824_SBAS673.gif
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D826_SBAS673.gif
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D828_SBAS673.gif
Figure 28. Performance vs Clock Amplitude (150 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D830_SBAS673.gif
Figure 30. Performance vs Clock Duty Cycle (150 MHz)

7.16 Typical Characteristics: ADC3422

Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3421 ADC3422 ADC3423 ADC3424 D601_SBAS673.gif
SFDR = 89 dBc, SNR = 70.9 dBFS, SINAD = 70.8 dBFS,
THD = 88 dBc, HD2 = 110 dBc, HD3 = 89 dBc
Figure 31. FFT for 10-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D603_SBAS673.gif
SFDR = 101 dBc, SNR = 70.6 dBFS, SINAD = 70.5 dBFS,
THD = 98 dBc, HD2 = 106 dBc, HD3 = 101 dBc
Figure 33. FFT for 70-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D605_SBAS673.gif
SFDR = 86 dBc, SNR = 69.9 dBFS, SINAD = 69.8 dBFS,
THD = 85 dBc, HD2 = 93 dBc, HD3 = 86 dBc
Figure 35. FFT for 170-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D607_SBAS673.gif
SFDR = 75 dBc, SNR = 69 dBFS, SINAD = 67.9 dBFS,
THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc
Figure 37. FFT for 270-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D609_SBAS673.gif
SFDR = 68 dBc, SNR = 67.2 dBFS, SINAD = 67.1 dBFS,
THD = –86 dBc, HD2 = 75 dBc, HD3 = 73 dBc
Figure 39. FFT for 450-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D611_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 102 dBFS,
each tone at –7 dBFS
Figure 41. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D613_SBAS673.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 95 dBFS,
each tone at –7 dBFS
Figure 43. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D615_SBAS673.gif
Figure 45. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D617_SBAS673.gif
Figure 47. Signal-to-Noise Ratio vs Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D619_SBAS673.gif
Figure 49. Performance vs Input Amplitude (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D621_SBAS673.gif
Figure 51. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D623_SBAS673.gif
Figure 53. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D625_SBAS673.gif
Figure 55. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D627_SBAS673.gif
Figure 57. Performance vs Clock Amplitude (40 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D629_SBAS673.gif
Figure 59. Performance vs Clock Duty Cycle (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D602_SBAS673.gif
SFDR = 85 dBc, SNR = 71.2 dBFS, SINAD = 70.9 dBFS,
THD = 83 dBc, HD2 = 92 dBc, HD3 = 85 dBc
Figure 32. FFT for 10-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D604_SBAS673.gif
SFDR = 90 dBc, SNR = 70.8 dBFS, SINAD = 70.6 dBFS,
THD = 87 dBc, HD2 = 91 dBc, HD3 = 90 dBc
Figure 34. FFT for 70-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D606_SBAS673.gif
SFDR = 85 dBc, SNR = 70.1 dBFS, SINAD = 70 dBFS,
THD = 86 dBc, HD2 = 85 dBc ,HD3 = 112 dBc
Figure 36. FFT for 170-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D608_SBAS673.gif
SFDR = 75 dBc, SNR = 69.2 dBFS, SINAD = 67.9 dBFS,
THD = 73 dBc, HD2 = 75 dBc, HD3 = 81 dBc
Figure 38. FFT for 270-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D610_SBAS673.gif
SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.4 dBFS,
THD = –87 dBc, HD2 = –68 dBc, HD3 = –87 dBc
Figure 40. FFT for 450-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D612_SBAS673.gif
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 110 dBFS,
each tone at –36 dBFS
Figure 42. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D614_SBAS673.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 44. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D616_SBAS673.gif
Figure 46. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D618_SBAS673.gif
Figure 48. Spurious-Free Dynamic Range vs
Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D620_SBAS673.gif
Figure 50. Performance vs Input Amplitude (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D622_SBAS673.gif
Figure 52. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D624_SBAS673.gif
Figure 54. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D626_SBAS673.gif
Figure 56. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D628_SBAS673.gif
Figure 58. Performance vs Clock Amplitude (150 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D630_SBAS673.gif
Figure 60. Performance vs Clock Duty Cycle (150 MHz)

7.17 Typical Characteristics: ADC3423

Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3421 ADC3422 ADC3423 ADC3424 D401_SBAS673.gif
SFDR = 89 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 89 dBc, HD2 = 108 dBc, HD3 = 89 dBc
Figure 61. FFT for 10-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D403_SBAS673.gif
SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS,
THD = 91 dBc, HD2 = 112 dBc, HD3 = 92 dBc
Figure 63. FFT for 70-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D405_SBAS673.gif
SFDR = 87 dBc, SNR = 70.2 dBFS, SINAD = 70.1 dBFS,
THD = 93 dBc, HD2 = 102 dBc, HD3 = 87 dBc
Figure 65. FFT for 170-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D407_SBAS673.gif
SFDR = 76 dBc, SNR = 69.2 dBFS, SINAD = 68.3 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc
Figure 67. FFT for 270-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D409_SBAS673.gif
SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.1 dBFS,
THD = 77 dBc, HD2 = 68 dBc, HD3 = 89 dBc
Figure 69. FFT for 450-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D411_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 98 dBFS,
each tone at –7 dBFS
Figure 71. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D413_SBAS673.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 90 dBFS,
each tone at –7 dBFS
Figure 73. FFT FOR Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D415_SBAS673.gif
Figure 75. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D417_SBAS673.gif
Figure 77. Signal-to-Noise Ratio vs Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D419_SBAS673.gif
Figure 79. Performance vs Input Amplitude (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D421_SBAS673.gif
Figure 81. Performance vs Input Common-Mode Voltage
(30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D423_SBAS673.gif
Figure 83. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D425_SBAS673.gif
Figure 85. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D427_SBAS673.gif
Figure 87. Performance vs Clock Amplitude (40 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D429_SBAS673.gif
Figure 89. Performance vs Clock Duty cycle (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D402_SBAS673.gif
SFDR = 84 dBc, SNR = 70.9 dBFS, SINAD = 70.7 dBFS,
THD = 83 dBc, HD2 = 92 dBc, HD3 = 84 dBc
Figure 62. FFT for 10-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D404_SBAS673.gif
SFDR = 86 dBc, SNR = 70.7 dBFS, SINAD = 70.5 dBFS,
THD = 84 dBc, HD2 = 92 dBc, HD3 = 86 dBc
Figure 64. FFT for 70-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D406_SBAS673.gif
SFDR = 86 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS,
THD = 88 dBc, HD2 = 86 dBc, HD3 = 97 dBc
Figure 66. FFT for 170-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D408_SBAS673.gif
SFDR = 75 dBc, SNR = 69.5 dBFS, SINAD = 68.4 dBFS,
THD = 75 dBc, HD2 = 75 dBc, HD3 = 82 dBc
Figure 68. FFT for 270-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D410_SBAS673.gif
SFDR = 67 dBc SNR = 67.7 dBFS, SINAD = 67.3 dBFS,
THD = 77 dBc, HD2 = 67 dBc, HD3 = 84 dBc
Figure 70. FFT for 450-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D412_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 72. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D414_SBAS673.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 74. FFT FOR Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D416_SBAS673.gif
Figure 76. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D418_SBAS673.gif
Figure 78. Spurious-Free Dynamic Range vs
Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D420_SBAS673.gif
Figure 80. Performance vs Input Amplitude (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D422_SBAS673.gif
Figure 82. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D424_SBAS673.gif
Figure 84. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D426_SBAS673.gif
Figure 86. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D428_SBAS673.gif
Figure 88. Performance vs Clock Amplitude (150 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D430_SBAS673.gif
Figure 90. Performance vs Clock Duty Cycle (150 MHz)

7.18 Typical Characteristics: ADC3424

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3421 ADC3422 ADC3423 ADC3424 D201_SBAS673.gif
SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS,
THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc
Figure 91. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D203_SBAS673.gif
SFDR = 99 dBc, SNR = 70.3 dBFS, SINAD = 70.3 dBFS,
THD = 95 dBc, HD2 = 103 dBc, HD3 = 99 dBc
Figure 93. FFT for 70-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D205_SBAS673.gif
SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS,
THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc
Figure 95. FFT for 170-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D207_SBAS673.gif
SFDR = 76 dBc, SNR = 68.94 dBFS, SINAD = 68.4 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc
Figure 97. FFT for 270-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D209_SBAS673.gif
SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS,
THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc
Figure 99. FFT for 450-MHz Input Signal (Dither On)
ADC3421 ADC3422 ADC3423 ADC3424 D211_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 100 dBFS,
each tone at –7 dBFS
Figure 101. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D213_SBAS673.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86 dBFS,
each tone at –7 dBFS
Figure 103. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D215_SBAS673.gif
Figure 105. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D217_SBAS673.gif
Figure 107. Signal-to-Noise Ratio vs Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D219_SBAS673.gif
Figure 109. Performance vs Input Amplitude (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D221_SBAS673.gif
Figure 111. Performance vs Input Common-Mode Voltage (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D223_SBAS673.gif
Figure 113. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D225_SBAS673.gif
Figure 115. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D227_SBAS673.gif
Figure 117. Performance vs Clock Amplitude (40 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D229_SBAS673.gif
Figure 119. Performance vs Clock Duty Cycle (30 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D202_SBAS673.gif
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc
Figure 92. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D204_SBAS673.gif
SFDR = 91 dBc, SNR = 70.6 dBFS, SINAD = 70.6 dBFS,
THD = 87 dBc, HD2 = 91 dBc, HD3 = 95 dBc
Figure 94. FFT for 70-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D206_SBAS673.gif
SFDR = 85 dBc, SNR = 70.3 dBFS, SINAD = 70.2 dBFS,
THD = 88 dBc, HD2 = 99 dBc, HD3 = 85 dBc
Figure 96. FFT for 170-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D208_SBAS673.gif
SFDR = 76 dBc, SNR = 69.3 dBFS, SINAD = 68.6 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 82 dBc
Figure 98. FFT for 270-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D210_SBAS673.gif
SFDR = 69 dBc, SNR = 67.8 dBFS, SINAD = 66.8 dBFS,
THD = 73 dBc, HD2 = 77 dBc, HD3 = 69 dBc
Figure 100. FFT for 450-MHz Input Signal (Dither Off)
ADC3421 ADC3422 ADC3423 ADC3424 D212_SBAS673.gif
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 99 dBFS,
each tone at –36 dBFS
Figure 102. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D214_SBAS673.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 102 dBFS,
each tone at –36 dBFS
Figure 104. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D216_SBAS673.gif
Figure 106. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D218_SBAS673.gif
Figure 108. Spurious-Free Dynamic Range vs
Input Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D220_SBAS673.gif
Figure 110. Performance vs Input Amplitude (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D222_SBAS673.gif
Figure 112. Performance vs Input Common-Mode Voltage (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D224_SBAS673.gif
Figure 114. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D226_SBAS673.gif
Figure 116. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D228_SBAS673.gif
Figure 118. Performance vs Clock Amplitude (150 MHz)
ADC3421 ADC3422 ADC3423 ADC3424 D230_SBAS673.gif
Figure 120. Performance vs Clock Duty Cycle (150 MHz)

7.19 Typical Characteristics: Common

Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
ADC3421 ADC3422 ADC3423 ADC3424 D001_SBAS673.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 121. Power-Supply Rejection Ratio vs
Test Signal Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D003_SBAS673.gif
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
Figure 123. Common-Mode Rejection Ratio vs
Test Signal Frequency
ADC3421 ADC3422 ADC3423 ADC3424 D009_SBAS673.gif
Figure 125. Power vs Sampling Frequency
(Two-Wire Mode)
ADC3421 ADC3422 ADC3423 ADC3424 D002_SBAS673.gif
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP,
SINAD = 58.51 dBFS, SFDR = 60 dBc
Figure 122. Power-Supply Rejection Ratio Spectrum
ADC3421 ADC3422 ADC3423 ADC3424 D004_SBAS673.gif
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP,
SINAD = 69.66 dBFS, SFDR = 75 dBc
Figure 124. Common-Mode Rejection Ratio Spectrum
ADC3421 ADC3422 ADC3423 ADC3424 D010_SBAS673.gif
Figure 126. Power vs Sampling Frequency
(One-Wire Mode)

7.20 Typical Characteristics: Contour

Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when is chopper enabled, unless otherwise noted.
ADC3421 ADC3422 ADC3423 ADC3424 SFDR_SBAS673.png Figure 127. Spurious-Free Dynamic Range (SFDR)
ADC3421 ADC3422 ADC3423 ADC3424 SNR_SBAS673.png Figure 128. Signal-to-Noise Ratio (SNR)