SBAS988 November   2023 ADC34RF55

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 5.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Bandwidth and Full-Scale
        2. 6.3.1.2 Input Imbalance
        3. 6.3.1.3 Over Range Indication
        4. 6.3.1.4 Analog out-of-band dither
      2. 6.3.2 Sampling Clock Input
      3. 6.3.3 ADC Foreground Calibration
        1. 6.3.3.1 Calibration Control
        2. 6.3.3.2 ADC Switch
        3. 6.3.3.3 Calibration Configuration
      4. 6.3.4 SYSREF
        1. 6.3.4.1 SYSREF Capture Detection
      5. 6.3.5 Decimation Filter
        1. 6.3.5.1 Decimation Filter Response
        2. 6.3.5.2 Decimation Filter Configuration
        3. 6.3.5.3 20-bit Output Mode
        4. 6.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 6.3.5.5 NCO Frequency Programming Using the SPI Interface
        6. 6.3.5.6 Fast Frequency Hopping
          1. 6.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 6.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 6.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 6.3.6.1.1 SYNC Signal
        2. 6.3.6.2 JESD204B Frame Assembly
          1. 6.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 6.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 6.3.6.2.3 JESD204B Frame Assembly with Complex Decimation - Single Band
          4. 6.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 6.3.6.3 SERDES Output MUX
      7. 6.3.7 Test Pattern
        1. 6.3.7.1 Transport Layer
        2. 6.3.7.2 Link Layer
        3. 6.3.7.3 Internal Capture Memory Buffer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Bypass Mode
      2. 6.4.2 Digital Averaging
    5. 6.5 Programming
      1. 6.5.1 GPIO Pin Control
      2. 6.5.2 Configuration using the SPI interface
        1. 6.5.2.1 Register Write
        2. 6.5.2.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Detailed Register Description
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Wideband RF Sampling Receiver
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Clocking
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Sampling Clock
      4. 7.2.4 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Initial Device Configuration After Power-Up
        1. 7.3.1.1  STEP 1: RESET
        2. 7.3.1.2  STEP 2: Device Configuration
        3. 7.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 7.3.1.4  STEP 4: SYSREF Synchronization
        5. 7.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 7.3.1.6  STEP 6: Analog Trim Settings
        7. 7.3.1.7  STEP 7: Calibration Configuration
        8. 7.3.1.8  STEP 8: SYSREF Synchronization
        9. 7.3.1.9  STEP 9: Run Power up Calibration
        10. 7.3.1.10 Step 10: JESD Interface Synchronization
        11. 7.3.1.11 Step 11: NCO Configuration
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.7 Test Pattern

The ADC34RF55 provides several different options to output test patterns instead of the actual output data of the ADC to simplify the serial interface and system debug of the JESD204B digital interface link. The output data path is shown in Figure 6-44.

GUID-20201008-CA0I-VDLD-WQFH-BJXF012SVV7V-low.gifFigure 6-44 Test Pattern Options

The available test patterns in each block are described in Table 6-41. Both test pattern blocks replace output data from the digital block (and not from the ADC) and are available in decimation or decimation bypass mode.

Table 6-41 Test Pattern Overview
TEST PATTERN LOCATIONTYPE8b/10b encodedREGISTER PAGEREGISTER
TRANSPORT LAYERCUSTOM PATTERNYesJESD
0x05 0x04		0x2E, D0
TOGGLE 1010 PATTERNYes0x2E, D1
RAMP PATTERNYes0x2E, D2
LINK LAYERJESD204B TEST PATTERNSDepends0x2D, D2-D0
PRBS PATTERN (27.. 231)No0x2F, D6-D4

The RAMP pattern provides two different output options. Internally each ADC data bus consists of parallel data streams. The RAMP pattern is generated for each stream and a different starting value can be set for each stream. By default all starting values are 0 and increment =1. For example, DDC bypass mode uses 2 internal data streams per ADC channel. Enabling a RAMP pattern would show a 'slow' ramp which increments once every 2 clock cycles with starting values set to 0 and ramp increment = 1.

On the other hand a RAMP pattern, which increments every clock cycle, can be set using different starting values (e.g. 0/1) for the 2 streams and setting the RAMP increment to 2. Table Table 6-42 shows the register addresses for the different digital streams being used for each operating mode.

Table 6-42 Register address for RAMP starting values based on operating mode
Address
(JESD Page)		Bypass Mode
LMFS = 8-4-2-2		Complex Decimation
Single Band		Complex Decimation
Dual Band
0xA4/A5/A6A0A1I0A1I0
0xA8/A9/AAA1A1Q0A1Q0
0xAC/AD/AEA2I0
0xB0/B1/B2A2Q0
0xB4/B5/B6B0B1I0B1I0
0xB8/B9/BAB1B1Q0B2Q0
0xBC/BD/BEB2I0
0xC0/C1/C2B2Q0
0xC4/C5/C6C0C1I0C1I0
0xC8/C9/CAC1C1Q0C1Q0
0xCC/CD/CEC2I0
0xD0/D1/D2C2Q0
0xD4/D5/D6D0D1I0D1I0
0xD8/D9/DAD1D1Q0D1Q0
0xDC/DD/DED2I0
0xE0/E1/E2D2Q0