SBAS988 November   2023 ADC34RF55

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 5.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Bandwidth and Full-Scale
        2. 6.3.1.2 Input Imbalance
        3. 6.3.1.3 Over Range Indication
        4. 6.3.1.4 Analog out-of-band dither
      2. 6.3.2 Sampling Clock Input
      3. 6.3.3 ADC Foreground Calibration
        1. 6.3.3.1 Calibration Control
        2. 6.3.3.2 ADC Switch
        3. 6.3.3.3 Calibration Configuration
      4. 6.3.4 SYSREF
        1. 6.3.4.1 SYSREF Capture Detection
      5. 6.3.5 Decimation Filter
        1. 6.3.5.1 Decimation Filter Response
        2. 6.3.5.2 Decimation Filter Configuration
        3. 6.3.5.3 20-bit Output Mode
        4. 6.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 6.3.5.5 NCO Frequency Programming Using the SPI Interface
        6. 6.3.5.6 Fast Frequency Hopping
          1. 6.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 6.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 6.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 6.3.6.1.1 SYNC Signal
        2. 6.3.6.2 JESD204B Frame Assembly
          1. 6.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 6.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 6.3.6.2.3 JESD204B Frame Assembly with Complex Decimation - Single Band
          4. 6.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 6.3.6.3 SERDES Output MUX
      7. 6.3.7 Test Pattern
        1. 6.3.7.1 Transport Layer
        2. 6.3.7.2 Link Layer
        3. 6.3.7.3 Internal Capture Memory Buffer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Bypass Mode
      2. 6.4.2 Digital Averaging
    5. 6.5 Programming
      1. 6.5.1 GPIO Pin Control
      2. 6.5.2 Configuration using the SPI interface
        1. 6.5.2.1 Register Write
        2. 6.5.2.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Detailed Register Description
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Wideband RF Sampling Receiver
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Clocking
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Sampling Clock
      4. 7.2.4 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Initial Device Configuration After Power-Up
        1. 7.3.1.1  STEP 1: RESET
        2. 7.3.1.2  STEP 2: Device Configuration
        3. 7.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 7.3.1.4  STEP 4: SYSREF Synchronization
        5. 7.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 7.3.1.6  STEP 6: Analog Trim Settings
        7. 7.3.1.7  STEP 7: Calibration Configuration
        8. 7.3.1.8  STEP 8: SYSREF Synchronization
        9. 7.3.1.9  STEP 9: Run Power up Calibration
        10. 7.3.1.10 Step 10: JESD Interface Synchronization
        11. 7.3.1.11 Step 11: NCO Configuration
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 RTD Package, 64 Pin QFN (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
ANALOG INPUTS
INAP 14 I Differential analog input for channel A. 100 Ω differential internal termination.
INAM 15
INBP 18 I Differential analog input for channel B. 100 Ω differential internal termination.
INBM 19
INCP 35 I Differential analog input for channel C. 100 Ω differential internal termination.
INCM 34
INDP 31 I Differential analog input for channel D. 100 Ω differential internal termination.
INDM 30
VCM 26 O Common-mode voltage output for the analog inputs.
CLOCK, SYNCHRONIZATION
CLKP 23 I Differential sampling clock input. 100 Ω differential internal termination.
CLKM 24
SYSREFP 27 I Differential external synchronization input.
SYSREFM 28
CONTROL
RESETb 11 I Hardware reset. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18.
SEN 57 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD18.
SCLK 55 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO 56 I/O Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
GPIO1 39 I/O GPIO control pin. This pin is configured through SPI interface for power down or NCO control function.
GPIO2 38 I/O GPIO control pin. This pin is configured through SPI interface for power down or NCO control function.
SPISEL 10 I Determines the functional of the SPI interface pins: either normal SPI for register programming or fast access to NCO selection only for fast frequency hopping.
DIGITAL DATA INTERFACE
DOUT0P 4 O JESD204B high-speed serial data output interface pins for channels A to D.

Output lanes can be reordered using the output MUX.
DOUT0M 5
DOUT1P 1 O
DOUT1M 2
DOUT2P 63 O
DOUT2M 64
DOUT3P 60 O
DOUT3M 61
DOUT4P 45 O
DOUT4M 44
DOUT5P 48 O
DOUT5M 47
DOUT6P 50 O
DOUT6M 49
DOUT7P 53 O
DOUT7M 52
POWER SUPPLY
AVDD18 17,20,29,32, 58 I Analog 1.8-V power supply
AVDD12 13,16,21,33, 36 I Analog 1.2-V power supply
CLKVDD 25 I Clock 1.2-V power supply. Very sensitive to power supply noise. Directly impacts close in aperture phase noise.
DVDD 3,7,9,40,42, 46,54,59 I Digital 1.2-V power supply
AGND 12,37 I Analog ground, shorted to thermal pad.
CLKGND 22 I Clock ground.
DGND 6,8,41,43,51,62 I Digital ground.