SBASA45
December 2022
ADC3544
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics - Power Consumption
6.6
Electrical Characteristics - DC Specifications
6.7
Electrical Characteristics - AC Specifications
6.8
Timing Requirements
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Analog Input
8.3.1.1
Analog Input Bandwidth
8.3.1.2
Analog Front End Design
8.3.1.2.1
Sampling Glitch Filter Design
8.3.1.2.2
Single Ended Input
8.3.1.2.3
Analog Input Termination and DC Bias
8.3.1.2.3.1
AC-Coupling
8.3.1.2.3.2
DC-Coupling
8.3.2
Clock Input
8.3.2.1
Single Ended vs Differential Clock Input
8.3.3
Voltage Reference
8.3.3.1
Internal voltage reference
8.3.3.2
External voltage reference (VREF)
8.3.3.3
External voltage reference with internal buffer (REFBUF)
8.3.4
Digital Down Converter
8.3.4.1
Digital Filter Operation
8.3.4.2
FS/4 Mixing with Real Output
8.3.4.3
Numerically Controlled Oscillator (NCO) and Digital Mixer
8.3.4.4
Decimation Filter
8.3.4.5
SYNC
8.3.4.6
Output Formatting with Decimation
8.3.4.6.1
Parallel CMOS
8.3.4.6.2
Serialized CMOS Interface
8.3.5
Digital Interface
8.3.5.1
Parallel CMOS Output
8.3.5.2
Serialized CMOS output
8.3.5.2.1
SDR Output Clocking
8.3.5.3
Output Data Format
8.3.5.4
Output Formatter
8.3.5.5
Output Bit Mapper
8.3.5.6
Output Interface/Mode Configuration
8.3.5.6.1
Configuration Example
8.3.6
Test Pattern
8.4
Device Functional Modes
8.4.1
Normal operation
8.4.2
Power Down Options
8.5
Programming
8.5.1
Configuration using PINs only
8.5.2
Configuration using the SPI interface
8.5.2.1
Register Write
8.5.2.2
Register Read
8.6
Register Maps
8.6.1
Detailed Register Description
9
Application Information Disclaimer
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Input Signal Path
9.2.2.2
Sampling Clock
9.2.2.3
Voltage Reference
9.2.3
Application Curves
9.3
Initialization Set Up
9.3.1
Register Initialization During Operation
9.4
Power Supply Recommendations
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Trademarks
10.3
Electrostatic Discharge Caution
10.4
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSB|40
MPQF185C
Thermal pad, mechanical data (Package|Pins)
RSB|40
QFND255H
Orderable Information
sbasa45_oa
sbasa45_pm
4
Revision History
DATE
REVISION
NOTES
December 2022
*
Initial release.