SBASA45 December   2022 ADC3544

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics - AC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density No input signal -153 dBFS/Hz
SNR Signal to noise ratio fIN = 5 MHz 71.5 74.0 dBFS
fIN = 10 MHz 73.9
fIN = 40 MHz 73.0
fIN = 70 MHz 70.6
fIN = 100 MHz 69.2
SINAD Signal to noise and distortion ratio fIN = 5 MHz 71 74.0 dBFS
fIN = 10 MHz 73.9
fIN = 40 MHz 73.0
fIN = 70 MHz 70.6
fIN = 100 MHz 69.2
ENOB Effective number of bits fIN = 5 MHz 11.5 12.0 bit
fIN = 10 MHz 11.9
fIN = 40 MHz 11.9
fIN = 70 MHz 11.8
fIN = 100 MHz 11.7
THD Total Harmonic Distortion (First five harmonics) fIN = 5 MHz 75 82 dBc
fIN = 10 MHz 81
fIN = 40 MHz 80
fIN = 70 MHz 75
fIN = 100 MHz 72
HD2 Second Harmonic Distortion fIN = 5 MHz 80 85 dBc
fIN = 10 MHz 82
fIN = 40 MHz 83
fIN = 70 MHz 79
fIN = 100 MHz 72
HD3 Third Harmonic Distortion fIN = 5 MHz 77 90 dBc
fIN = 10 MHz 96
fIN = 40 MHz 92
fIN = 70 MHz 82
fIN = 100 MHz 83
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 5 MHz 90 93 dBFS
fIN = 10 MHz 94
fIN = 40 MHz 89
fIN = 70 MHz 85
fIN = 100 MHz 83
IMD3 Two tone inter-modulation distortion f1 = 10 MHz, f2 = 12 MHz, AIN = -7 dBFS/tone 93 dBc