The ADC3644 device is a low-noise, ultra-low power, 14-bit, 125-MSPS dual-channel, high-speed analog-to-digital converter (ADC). Designed for low power consumption, the device delivers a noise spectral density of –153 dBFS/Hz, combined with very good linearity and dynamic range. The ADC3644 offers IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 82 mW/ch at 125 MSPS, and power consumption scales well with lower sampling rates.
The ADC3644 use a DDR or a serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to 105⁰C.
PART NUMBER (1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC3644 | WQFN (40) | 5.00 × 5.00 mm |
PART NUMBER | RESOLUTION | SAMPLING RATE |
---|---|---|
ADC3641 | 14-BIT | 10 MSPS |
ADC3642 | 14-BIT | 25 MSPS |
ADC3643 | 14-BIT | 65 MSPS |
ADC3644 | 14-BIT | 125 MSPS |
DATE | REVISION | NOTES |
---|---|---|
May 2022 | * | Initial Release |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT/REFERENCE | |||
AINM | 13 | I | Negative analog input, channel A |
AINP | 12 | I | Positive analog input, channel A |
BINP | 39 | I | Positive analog input, channel B |
BINM | 38 | I | Negative analog input, channel B |
REFBUF | 4 | I | 1.2 V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions. |
REFGND | 3 | I | Reference ground input, 0 V |
VCM | 8 | O | Common-mode voltage output for the analog inputs, 0.95 V. |
VREF | 2 | I | External voltage reference input, 1.6 V |
CLOCK | |||
CLKM | 7 | I | Negative differential sampling clock input for the ADC |
CLKP | 6 | I | Positive differential sampling clock input for the ADC |
CONFIGURATION | |||
PDN/SYNC | 1 | I | Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor. |
RESET | 9 | I | Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor. |
SCLK | 35 | I | Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor. |
SDIO | 10 | I | Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor. |
SEN | 16 | I | Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD. |
DIGITAL INTERFACE | |||
DA0 | 17 | O | CMOS digital data output. |
DA1 | 18 | I/O | CMOS digital data output. Used as FCLK frame clock output for serialized CMOS output modes. Configured using SPI. |
DA2 | 19 | O | CMOS digital data output. |
DA3 | 20 | O | CMOS digital data output. |
DA4 | 22 | O | CMOS digital data output. |
DA5 | 23 | O | CMOS digital data output. |
DA6 | 24 | O | CMOS digital data output. |
DB0 | 34 | O | CMOS digital data output. |
DB1 | 33 | I/O | CMOS digital data output. Used as DCLKIN bit clock input for serialized CMOS output modes. Configured using SPI. |
DB2 | 32 | O | CMOS digital data output. |
DB3 | 31 | O | CMOS digital data output. |
DB4 | 29 | O | CMOS digital data output. |
DB5 | 28 | O | CMOS digital data output. |
DB6 | 27 | O | CMOS digital data output. |
DCLK | 25 | O | CMOS output for data bit clock. |
POWER SUPPLY | |||
AVDD | 5,15,36 | I | Analog 1.8-V power supply |
GND | 11,14,37,40, PowerPAD™ | I | Ground, 0 V |
IOGND | 26 | I | Ground, 0 V for digital interface |
IOVDD | 21,30 | I | 1.8-V power supply for digital interface |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT |
---|---|---|---|---|
Supply voltage range, AVDD, IOVDD | –0.3 | 2.1 | V | |
Supply voltage range, GND, IOGND, REFGND | –0.3 | 0.3 | V | |
Voltage applied to input pins | AINP/M, BINP/M, CLKP/M, VREF, REFBUF | –0.3 | MIN(2.1, AVDD+0.3) | V |
PDN, RESET, SCLK, SEN, SDIO | –0.3 | MIN(2.1, AVDD+0.3) | ||
DB1 (DCLKIN) | –0.3 | MIN(2.1, IOVDD+0.3) | ||
Junction temperature, TJ | 105 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 2500 | V |
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | 1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Supply voltage range | AVDD(1) | 1.75 | 1.8 | 1.85 | V | |
IOVDD(1) | 1.75 | 1.8 | 1.85 | V | ||
TA | Operating free-air temperature | –40 | 105 | °C | ||
TJ | Operating junction temperature | 105(2) | °C |
THERMAL METRIC(1) | ADC3644 | UNIT | |
---|---|---|---|
RSB (QFN) | |||
40 Pins | |||
RΘJA | Junction-to-ambient thermal resistance | 30.7 | °C/W |
RΘJC(top) | Junction-to-case (top) thermal resistance | 16.4 | °C/W |
RΘJB | Junction-to-board thermal resistance | 10.5 | °C/W |
ΨJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ΨJB | Junction-to-board characterization parameter | 10.5 | °C/W |
RΘJC(bot) | Junction-to-case (bottom) thermal resistance | 2.0 | °C/W |