SBASA01B September   2020  – March 2022 ADC3660

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 SDR Output Clocking
        2. 8.3.5.2 Output Data Format
        3. 8.3.5.3 Output Formatter
        4. 8.3.5.4 Output Bit Mapper
        5. 8.3.5.5 Output Interface/Mode Configuration
          1. 8.3.5.5.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-D9E1F570-A76B-4210-94AB-8CC82AAAEF43-low.gifFigure 5-1 RSB Package, 40-Pin WQFN
(Top View)
Table 5-1 Pin Descriptions
PINI/ODescription
NameNo.
INPUT/REFERENCE
AINP12IPositive analog input, channel A
AINM13INegative analog input, channel A
BINP39IPositive analog input, channel B
BINM38INegative analog input, channel B
VCM8OCommon-mode voltage output for the analog inputs, 0.95 V
VREF2IExternal voltage reference input, 1.6 V
REFBUF4I1.2V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND3IReference ground input, 0 V
CLOCK
CLKP6IPositive differential sampling clock input for the ADC
CLKM7INegative differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC1IPower down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET9IHardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SEN16ISerial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
SCLK35ISerial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO10I/OSerial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
NC17,19,20,22, 29,31,32,34-Do not connect
DIGITAL INTERFACE
DA624OCMOS data output.
DA523OCMOS data output
FCLK18OCMOS frame clock output
DB627OCMOS data output.
DB528OCMOS data output
DCLKIN33ICMOS bit clock input
DCLK25OCMOS bit clock output
POWER SUPPLY
AVDD5,15,36IAnalog 1.8V power supply
GND11,14,37,40, PowerPadIGround, 0V
IOVDD21,30I1.8V power supply for digital interface
IOGND26IGround, 0V for digital interface