SBASA01B September 2020 – March 2022 ADC3660
PRODUCTION DATA
In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled via SPI register writes (0x14/0x15/0x16). The test pattern generator is located after the decimation filter as shown in Figure 8-43. In decimation mode (real and complex), the test patterns replace the output data from the DDC - however channel A controls the test patterns for both channels.