SBASA01B September 2020 – March 2022 ADC3660
PRODUCTION DATA
The following sequence summarizes all the relevant registers for changing the output interface and/or enabling the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining steps can come in any order.
STEP | FEATURE | ADDRESS | DESCRIPTION | ||||
---|---|---|---|---|---|---|---|
1 | Output Interface | 0x07 | Select the output interface bit mapping depending on resolution and output interface. | ||||
Output Resolution | 2-wire | 1-wire | 1/2-wire | ||||
14-bit, 18-bit | 0x2B | 0x6C | 0x8D | ||||
16-bit, 20-bit | 0x4B | ||||||
2 | 0x13 | Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00 | |||||
3 | 0x0A/B/C | When changing the output interface bit mapper (0x07), the CMOS output buffer register has to be configured again. | |||||
4 | 0x18 | When changing the output interface bit mapper (0x07), the DCLKIN EN bit (D4) has to be set again. | |||||
5 | 0x19 | Configure the FCLK frequency based on bypass/decimation and number of lanes used. | |||||
Bypass/Dec | SCMOS | FCLK SRC (D7) | FCLK DIV (D4) | TOG FCLK (D0) | |||
Bypass/ Real Decimation | 2-wire | 0 | 1 | 0 | |||
1-wire | 0 | 0 | 0 | ||||
1/2-wire | 0 | 0 | 0 | ||||
Complex Decimation | 2-wire | 1 | 0 | 0 | |||
1-wire | 1 | 0 | 0 | ||||
1/2-wire | 0 | 0 | 1 | ||||
6 | 0x1B | Select the output interface resolution using the bit mapper (D5-D3). | |||||
7 | 0x1F | When changing the output interface bit mapper (0x07), the DCLKIN EN bit (D6) and DCLK OB EN (D4) have to be set again. | |||||
8 | 0x20 0x21 0x22 | Select the FCLK pattern for decimation for proper duty cycle output of the frame clock. | |||||
Output Resolution | 2-wire | 1-wire | 1/2-wire | ||||
Real Decimation | 14-bit | use default | 0xFE000 | use default | |||
16-bit | 0xFF000 | ||||||
18-bit | 0xFF800 | ||||||
20-bit | 0xFFC00 | ||||||
Complex Decimation | 14-bit | 0xFFFFF | 0xFFFFF | ||||
16-bit | |||||||
18-bit | |||||||
20-bit | |||||||
9 | 0x39..0x60 0x61..0x88 | Change output bit mapping for chA and chB if desired. This works also with the default interface selection. | |||||
10 | Decimation Filter | 0x24 | Enable the decimation filter | ||||
11 | 0x25 | Configure the decimation filter | |||||
12 | 0x2A/B/C/D 0x31/2/3/4 | Program the NCO frequency for complex decimation (can be skipped for real decimation) | |||||
13 | 0x27 0x2E | Configure the complex output data stream (set both bits to 0 for real decimation) | |||||
SCMOS | OP-Order (D4) | Q-Delay (D3) | |||||
2-wire | 1 | 0 | |||||
1-wire | 0 | 1 | |||||
1/2-wire | 1 | 1 | |||||
14 | 0x26 | Set the mixer gain and toggle the mixer reset bit to update the NCO frequency. |