SBASA01B September 2020 – March 2022 ADC3660
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
ADC TIMING SPECIFICATIONS | ||||||
tAD | Aperture Delay | 0.85 | ns | |||
tA | Aperture Jitter | square wave clock with fast edges | 180 | fs | ||
tJ | Jitter on DCLKIN | ± 50 | ps pk-pk | |||
tACQ | Signal acquisition period, Default | referenced to sampling clock falling edge | -TS/4 | Sampling Clock Period | ||
tCONV | Signal conversion period | referenced to sampling clock falling edge | 10 | ns | ||
Wake up time | Time to valid data after coming out of power down. Internal reference. | Bandgap reference enabled, single ended clock | 14.6 | us | ||
Bandgap reference enabled, differential clock | 14.0 | |||||
Bandgap reference disabled, single ended clock | 1.7 | ms | ||||
Bandgap reference disabled, differential clock | 2.1 | |||||
Time to valid data after coming out of power down. External 1.6V reference. | Bandgap reference enabled, single ended clock | 14.6 | us | |||
Bandgap reference enabled, differential clock | 14.0 | |||||
Bandgap reference disabled, single ended clock | 1.8 | ms | ||||
Bandgap reference disabled, differential clock | 1.7 | |||||
tS,SYNC | Setup time for SYNC input signal | Referenced to sampling clock rising edge | 500 | ps | ||
tH,SYNC | Hold time for SYNC input signal | 600 | ||||
ADC Latency | Signal input to data output | Serialized CMOS: 2-wire | 2 | ADC clock cycles | ||
Serialized CMOS: 1-wire | 1 | |||||
Serialized CMOS: 1/2-wire | 1 | |||||
Add. Latency | Real decimation by 2 | 21 | Output clock cycles | |||
Complex decimation by 2 | 22 | |||||
Real or complex decimation by 4, 8, 16, 32 | 23 | |||||
INTERFACE TIMING | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge |
2 + TDCLK + tCDCLK | 3 + TDCLK + tCDCLK | 4 + TDCLK + tCDCLK | ns |
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge |
2 + tCDCLK | 3 + tCDCLK | 4 + tCDCLK | |||
tCD | DCLK rising edge to output data delay 2-wire serial CMOS |
Fout = 10 MSPS, DA/B5,6 = 80 MBPS | -0.24 | 0.10 | ns | |
Fout = 20 MSPS, DA/B5,6 = 160 MBPS | -0.29 | 0.10 | ||||
Fout = 30 MSPS, DA/B5,6 = 240 MBPS | -0.28 | 0.09 | ||||
DCLK rising edge to output data delay 1-wire serial CMOS |
Fout = 5 MSPS, DA/B6 = 80 MBPS | -0.22 | 0.11 | |||
Fout = 10 MSPS, DA/B6 = 160 MBPS | -0.27 | 0.11 | ||||
Fout = 15 MSPS, DA/B6 = 240 MBPS | -0.52 | 0.08 | ||||
DCLK rising edge to output data delay 1/2-wire serial CMOS |
Fout = 5 MSPS, DA6 = 160 MBPS | -0.24 | 0.1 | |||
tDV | Data valid, 2-wire serial CMOS | Fout = 10 MSPS, DA/B5,6 = 80 MBPS | 12.19 | 12.36 | ns | |
Fout = 20 MSPS, DA/B5,6 = 160 MBPS | 5.93 | 6.1 | ||||
Fout = 30 MSPS, DA/B5,6 = 240 MBPS | 3.91 | 4.07 | ||||
Data valid, 1-wire serial CMOS | Fout = 5 MSPS, DA/B6 = 80 MBPS | 12.21 | 12.39 | |||
Fout = 10 MSPS, DA/B6 = 160 MBPS | 5.95 | 6.10 | ||||
Fout = 15 MSPS, DA/B6 = 240 MBPS | 3.83 | 4.08 | ||||
Data valid, 1/2-wire serial CMOS | Fout = 5 MSPS, DA6 = 160 MBPS | 5.36 | 6.13 | |||
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input | ||||||
fCLK,SCLK | Serial clock frequency | 20 | MHz | |||
tS,SEN | SEN falling edge to SCLK rising edge | 10 | ns | |||
tH,SEN | SCLK rising edge to SEN rising edge | 9 | ||||
tS,SDIO | SDIO setup time from rising edge of SCLK | 17 | ||||
tH,SDIO | SDIO hold time from rising edge of SCLK | 9 | ||||
SERIAL PROGRAMMING INTERFACE (SDIO) - Output | ||||||
tOZD | Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from tri-state to valid data | 3.9 | 10.8 | ns | ||
tODZ | Delay from SEN rising edge for SDIO transition from valid data to tri-state | 3.4 | 14 | |||
tOD | Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid | 3.9 | 10.8 |