SBASAP7 December 2024 ADC3664-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The ADC3664-SP includes a register (D2 of 0x11) to power down an internal DLL which increases the signal acquisition time for sample rates below 30MSPS from 25% to 50% of the clock period. When powering down the DLL, the acquisition time tracks the clock duty cycle.
SAMPLING CLOCK FS (MSPS) | DLL_PDN (D2 of 0x11) | ACQUISITION TIME (tACQ) |
---|---|---|
> 30 | 0 | TS / 4 |
≤ 30 | 1 | TS / 2 |