Figure 7-9 shows the location of the test pattern blocks within the device.
When the digital signal processing (DSP) features are disabled (D2
of 0x24), a test pattern block can be enabled to replace the ADC
data. Similarly, when using the DDC, a test pattern is available to
replace the DDC data.
Note: No test pattern block is available when the DSP features are
enabled and the DDC is not used.
Each test pattern block has the capability to
generate one of the following outputs:
- Ramp
pattern with programmable step size set by
PAT_DATA.
- Constant
pattern with a programmable custom pattern set by
PAT_DATA.
As shown in
Figure 7-9, there are two test pattern blocks, test pattern 0 and test
pattern 1. The test pattern mode for each block can be configured
via D7:D5 and D4:D2 of 0x16. A shared set of data bits (PAT_DATA) is
given to the test pattern blocks and this data is used as ramp
pattern step size and/or the constant pattern. The PAT_DATA is an
18-bit value located across three different registers: D17:D16 in
0x16, D15:D8 in 0x15, and D7:D0 in 0x14. The PAT_DATA is MSB
aligned. For example, if the device is configured for 14-bit
resolution and constant pattern, only the top 14-bits of the
PAT_DATA are used for the constant pattern. Additionally, in ramp
mode, the test pattern counter operates at a 18-bit resolution;
therefore, the ramp pattern step size must be configured based on
the desired resolution and the step size at that resolution.
Note: When not using the test pattern in the
DDC path. Only the top 14-bits of PAT_DATA are used.
Therefore, for higher resolutions, zeros are appended as
LSBs.
- The test pattern data must be configured to the following for
a step size of one at each resolution:
- 0x00001: 18-bit output
resolution
- 0x00004: 16-bit output
resolution
- 0x00010: 14-bit output
resolution