SBASAU9 October 2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
ADC TIMING SPECIFICATIONS | ||||||
tAD | Aperture Delay | 0.5 | ns | |||
tA | Aperture Jitter | square wave clock with fast edges | 250 | fs | ||
tACQ | Signal acquisition period, referenced to sampling clock falling edge | -TS/5 |
Sampling Clock Period | |||
tCONV | Signal conversion period, referenced to sampling clock falling edge | Fs = 25 MSPS | 5.5 | ns | ||
Fs = 65 MSPS | 5.5 | ns | ||||
Fs = 125 MSPS | 5.5 | ns | ||||
Wake up time | Time to valid data after coming out of power down. Internal reference. | 30 | us | |||
ADC Latency | Signal input to data output | DDR | 1 | ADC clock cycles | ||
SDR | 1 | |||||
INTERFACE TIMING - DDR CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | TS/4 + 3 | ns | |||
tDE | DCLK edge to previous data transition | Fs = 25 MSPS | -10 | -9 | ns | |
Fs = 65 MSPS | -3.8 | -3.4 | ||||
Fs = 125 MSPS | -2 | -1.8 | ||||
tDL | DCLK edge to next data transition | Fs = 25 MSPS | 9 | 10 | ||
Fs = 65 MSPS | 3.4 | 3.8 | ||||
Fs = 125 MSPS | 1.8 | 2 | ||||
INTERFACE TIMING - SDR CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | TS/4 + 3 | ns | |||
tDE | DCLK edge to previous data transition | Fs = 25 MSPS | -20 | -18 | ns | |
Fs = 65 MSPS | -7.6 | -6.9 | ||||
Fs = 125 MSPS | -4 | -3.6 | ||||
tDV | DCLK edge to next data transition | Fs = 25 MSPS | 18 | 20 | ||
Fs = 65 MSPS | 6.9 | 7.7 | ||||
Fs = 125 MSPS | 3.6 | 4 |