SBASAU9 October 2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125
PRODUCTION DATA
The ADC3908Dx and ADC3908Sx family supports parallel CMOS output modes - DDR (double data rate) and SDR (single data rate) output formats for dual and single channel devices, respectively. The output data can be configured to 2's complement (default) or offset binary via pin control (Interface configuration table). The device generates an output data clock and inverse data clock. For receivers that cannot use falling edge of data clock, inverse data clock can be used to clock data.