SNAS192G April 2003 – May 2016 ADCS7476 , ADCS7477 , ADCS7478
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VDD | P | Positive supply pin. These pins must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 0.1-µF and 1-µF monolithic capacitors placed within 1 cm of the power pin. ADCS747x uses this power supply as a reference, so it must be thoroughly bypassed. |
2 | GND | G | The ground return for the supply. |
3 | VIN | I | Analog input. This signal can range from 0 V to VDD. |
4 | SCLK | I | Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with ensured performance at 20 MHz. This clock directly controls the conversion and readout processes. |
5 | SDATA | O | Digital data output. The output words are clocked out of this pin by the SCLK pin. |
6 | CS | I | Chip select. A conversion process begins on the falling edge of CS. |