SBAS480C september   2009  – june 2023 ADS1000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog-to-Digital Converter
      2. 7.3.2 Clock Generator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Reset and Power Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 ADS1000-Q1 I2C Addresses
      3. 7.5.3 I2C General Call
      4. 7.5.4 I2C Data Rates
      5. 7.5.5 Output Code Calculation
    6. 7.6 Register Maps
      1. 7.6.1 Output Register
      2. 7.6.2 Configuration Register
      3. 7.6.3 Reading From the ADS1000-Q1
      4. 7.6.4 Writing to the ADS1000-Q1
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
        1. 8.1.1.1 Connecting Multiple Devices
        2. 8.1.1.2 Using GPIO Ports For I2C
        3. 8.1.1.3 Single-Ended Inputs
    2. 8.2 Typical Applications
      1. 8.2.1 ADS1000-Q1 With Current-Shunt Monitor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Part Selection
            1. 8.2.1.2.1.1 Gain Settings
            2. 8.2.1.2.1.2 Circuit Implementation
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Low-Side Current Measurement
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.4 I2C Data Rates

The I2C bus operates in one of three speed modes: standard, which allows a clock frequency of up to 100 kHz; fast, which allows a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode), which allows a clock frequency of up to 3.4 MHz. The ADS1000-Q1 is fully compatible with all three modes.

No special action must be taken to use the ADS1000-Q1 in standard or fast modes, but high-speed mode must be activated. To activate high-speed mode, send a special address byte of 00001XXXb following the start condition, where the XXX bits are unique to the Hs-capable controller. This byte is called the Hs controller code. (This byte is different from normal address bytes; the low bit does not indicate read/write status.) The ADS1000-Q1 does not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs controller code. On receiving a controller code, the ADS1000-Q1 switches on the high-speed mode filters, and communicates at up to 3.4 MHz. The ADS1000-Q1 switches out of Hs mode with the next stop condition.

For more information on high-speed mode, consult the I2C specification.