SBAS444E May   2009  – December 2024 ADS1113 , ADS1114 , ADS1115

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: I2C
    7. 5.7 Typical Characteristics
  8. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator (ADS1114 and ADS1115 Only)
      8. 7.3.8 Conversion Ready Pin (ADS1114 and ADS1115 Only)
      9. 7.3.9 SMbus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
      3. 7.4.3 Duty Cycling For Low Power
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C General Call
        3. 7.5.1.3 I2C Speed Modes
      2. 7.5.2 Target Mode Operations
        1. 7.5.2.1 Receive Mode
        2. 7.5.2.2 Transmit Mode
      3. 7.5.3 Writing To and Reading From the Registers
      4. 7.5.4 Data Format
  10. 8 Registers
    1. 8.1 Register Map
      1. 8.1.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 8.1.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 8.1.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 8.1.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  11. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 Single-Ended Inputs
      3. 9.1.3 Input Protection
      4. 9.1.4 Unused Inputs and Outputs
      5. 9.1.5 Analog Input Filtering
      6. 9.1.6 Connecting Multiple Devices
      7. 9.1.7 Quick-Start Guide
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Shunt Resistor Considerations
        2. 9.2.2.2 Operational Amplifier Considerations
        3. 9.2.2.3 ADC Input Common-Mode Considerations
        4. 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 9.2.2.5 Noise and Input Impedance Considerations
        6. 9.2.2.6 First-Order RC Filter Considerations
        7. 9.2.2.7 Circuit Implementation
        8. 9.2.2.8 Results Summary
      3. 9.2.3 Application Curves
  12. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  13. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  14. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  15. 13Revision History
  16. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at VDD = 3.3V, data rate = 8SPS, and full-scale input voltage range (FSR) = ±2.048V (unless otherwise noted); maximum and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Common-mode input impedance FSR = ±6.144V(1) 10 MΩ
FSR = ±4.096V(1), FSR = ±2.048V 6
FSR = ±1.024V 3
FSR = ±0.512V, FSR = ±0.256V 100
Differential input impedance FSR = ±6.144V(1) 22 MΩ
FSR = ±4.096V(1) 15
FSR = ±2.048V 4.9
FSR = ±1.024V 2.4
FSR = ±0.512V, ±0.256V 710 kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes) 16 Bits
DR Data rate 8, 16, 32, 64, 128, 250, 475, 860 SPS
Data rate variation All data rates –10% 10%
Output noise See Noise Performance section
INL Integral nonlinearity DR = 8SPS, FSR = ±2.048V(2) 1 LSB
Offset error FSR = ±2.048V, differential inputs –3 ±1 3 LSB
FSR = ±2.048V, single-ended inputs ±3
Offset drift over temperature FSR = ±2.048V 0.005 LSB/°C
Long-term Offset drift FSR = ±2.048V, TA = 125°C,
1000 hours		 ±1 LSB
Offset power-supply rejection FSR = ±2.048V, DC supply variation 1 LSB/V
Offset channel match Match between any two inputs 3 LSB
Gain error(3) FSR = ±2.048V, TA = 25°C 0.01% 0.15%
Gain drift over temperature(3) FSR = ±0.256V 7 ppm/°C
FSR = ±2.048V 5 40
FSR = ±6.144V(1) 5
Long-term gain drift(3) FSR = ±2.048V, TA = 125°C,
1000 hours		 ±0.05%
Gain power-supply rejection 80 ppm/V
Gain match(3) Match between any two gains 0.02% 0.1%
Gain channel match Match between any two inputs 0.05% 0.1%
CMRR Common-mode rejection ratio At DC, FSR = ±0.256V 105 dB
At DC, FSR = ±2.048V 100
At DC, FSR = ±6.144V(1) 90
fCM = 60Hz, DR = 8SPS 105
fCM = 50Hz, DR = 8SPS 105
DIGITAL INPUT/OUTPUT
VIH High-level input voltage 0.7 VDD 5.5 V
VIL Low-level input voltage GND 0.3 VDD V
VOL Low-level output voltage IOL = 3mA GND 0.15 0.4 V
Input leakage current GND < VDIG < VDD –10 10 µA
POWER-SUPPLY
IVDD Supply current Power-down TA = 25°C 0.5 2 µA
5
Operating TA = 25°C 150 200
300
PD Power dissipation VDD = 5.0V 0.9 mW
VDD = 3.3 V 0.5
VDD = 2.0V 0.3
(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3V must be applied to the analog inputs of the device. See Table 7-1 for more information.
(2) Best-fit INL; covers 99% of full-scale
(3) Includes all errors from onboard PGA and voltage reference