SBASAV5 December   2023 ADS1114L , ADS1115L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
      7. 8.3.7 Digital Comparator
      8. 8.3.8 Conversion-Ready Pin
      9. 8.3.9 SMBus Alert Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C Interface Speed
          1. 8.5.1.2.1 Serial Clock (SCL) and Serial Data (SDA)
        3. 8.5.1.3 I2C Data Transfer Protocol
        4. 8.5.1.4 Timeout
        5. 8.5.1.5 I2C General-Call (Software Reset)
      2. 8.5.2 Reading and Writing Register Data
        1. 8.5.2.1 Reading Conversion Data or the Configuration Register
        2. 8.5.2.2 Writing the Configuration Register
      3. 8.5.3 Data Format
  10. 9 Register Map
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Unused Inputs and Outputs
      3. 10.1.3 Single-Ended Inputs
      4. 10.1.4 Input Protection
      5. 10.1.5 Analog Input Filtering
      6. 10.1.6 Connecting Multiple Devices
      7. 10.1.7 Duty Cycling For Low Power
      8. 10.1.8 I2C Communication Sequence Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Supply Sequencing
      2. 10.3.2 Power-Supply Decoupling
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at VDD = 3.3 V, data rate = 8 SPS, and full-scale input range (FSR) = ±2.048 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Common-mode input impedance FSR = ±6.144 V(1) 10 MΩ
FSR = ±4.096 V(1), FSR = ±2.048 V 6
FSR = ±1.024 V 3
FSR = ±0.512 V, FSR = ±0.256 V 100
Differential input impedance FSR = ±6.144 V(1) 22 MΩ
FSR = ±4.096 V(1) 15
FSR = ±2.048 V 4.9
FSR = ±1.024 V 2.4
FSR = ±0.512 V, FSR = ±0.256 V 710 kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes) 16 Bits
DR Data rate 8, 16, 32, 64, 128, 250, 475, 860 SPS
Data rate variation All data rates –10% 10%
INL Integral nonlinearity (best fit) DR = 8 SPS, FSR = ±2.048 V 1 LSB
Offset error (input referred) FSR = ±2.048 V, differential inputs –3 ±1 3 LSB
FSR = ±2.048 V, single-ended inputs ±3
Offset drift FSR = ±2.048 V 0.005 LSB/°C
Offset error match Between any two inputs 3 LSB
Gain error(2) TA = 25°C, FSR = ±2.048 V –0.15% ±0.01% 0.15%
Gain drift(2) FSR = ±0.256 V 7 ppm/°C
FSR = ±2.048 V 5 40
FSR = ±6.144 V 5
Gain error match Between any two gain settings –0.1% ±0.02% 0.1%
Between any two inputs –0.1% ±0.05% 0.1%
CMRR Common-mode rejection ratio At dc, FSR = ±0.256 V 105 dB
At dc, FSR = ±2.048 V 100
fCM = 50 Hz or 60 Hz, DR = 8 SPS 105
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low GND 0.25 V
VIH Logic input level, high 1 3.6 V
VOL Logic output level, low IOL = 3 mA GND 0.3 V
IOL Low-level output current VOL = 0.6 V 6 mA
Input current GND ≤ VDigital Input ≤ VDD –10 10 µA
Ci Capacitance Each pin 10 pF
SUPPLY CURRENT AND POWER DISSIPATION
IVDD Supply current Power-down 1.2 5 µA
Operating 150 300
PD Power dissipation VDD = 3.3 V 0.5 mW
VDD = 2.0 V 0.3
(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 3.6 V (whichever is smaller) must be
applied to this device. See Table 8-1 for more information.
(2) Includes all errors from onboard PGA, ADC, and voltage reference.