9.2.1.1 Design Requirements

9.2.1.2 Detailed Design Procedure

The biasing resistors R_B1 and R_B2 are used to set the common-mode voltage of the thermocouple to within the specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). If the application requires the thermocouple to be biased to GND, either a bipolar supply (for example, AVDD = 2.5 V and AVSS = –2.5 V) must be used for the device to meet the common-mode voltage requirement of the PGA, or the PGA must be bypassed. When choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ to 50 MΩ.

In addition to biasing the thermocouple, R_B1 and R_B2 are also useful for detecting an open thermocouple lead. When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition.

Although the device digital filter attenuates high-frequency components of noise, TI recommends providing a first-order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by R_F1, R_F2, and the differential capacitor C_DIF offers a cutoff frequency that is calculated using Equation 17.

Two common-mode filter capacitors (C_M1 and C_M2) are also added to offer attenuation of high-frequency, common-mode noise components. TI recommends that the differential capacitor C_DIF be at least an order of magnitude (10x) larger than the common-mode capacitors (C_M1 and C_M2) because mismatches in the common-mode capacitors can convert common-mode noise into differential noise.

The filter resistors R_F1 and R_F2 also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occur. Care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. TI recommends limiting the filter resistor values to below 1 kΩ.

The filter component values used in this design are: R_F1 = R_F2 = 1 kΩ, C_DIF = 100 nF, and C_CM1 = C_CM2 = 10 nF.

The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple voltage occurs at T_(TC) = 1250°C and is V_(TC) = 50.644 mV as defined in the tables published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature of T_(CJ) = 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at T_(TC) = 1250°C produces an output voltage of V_(TC) = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction temperature of T_(CJ) = –40°C. The maximum gain that can be applied when using the internal 2.048-V reference is then calculated as (2.048 V / 52.171 mV) = 39.3. The next smaller PGA gain setting the device offers is 32.

The device integrates a high-precision temperature sensor that can be used to measure the temperature of the cold junction. To measure the internal temperature of the ADS1120, the device must be set to internal temperature sensor mode by setting the TS bit to 1 in the configuration register. For best performance, careful board layout is critical to achieve good thermal conductivity between the cold junction and the device package.

However, the device does not perform automatic cold-junction compensation of the thermocouple. This compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one or multiple readings of the thermocouple voltage from the device and then sets the device to internal temperature sensor mode (TS = 1) to acquire the temperature of the cold junction. An algorithm similar to the following must be implemented on the microcontroller to compensate for the cold-junction temperature:

1. Measure the thermocouple voltage, V_(TC), between AIN0 and AIN1.
2. Measure the temperature of the cold junction, T_(CJ), using the temperature sensor mode of the ADS1120.
3. Convert the cold-junction temperature into an equivalent thermoelectric voltage, V_(CJ), using the tables or equations provided by NIST.
4. Add V_(TC) and V_(CJ) and translate the summation back into a thermocouple temperature using the NIST tables or equations again.

In some applications, the integrated temperature sensor of the ADS1120 cannot be used (for example, if the accuracy is not high enough or if the device cannot be placed close enough to the cold junction). The additional analog input channels of the device can be used in this case to measure the cold-junction temperature with a thermistor, RTD, or an analog temperature sensor.

The device is capable of 16-bit, noise-free resolution using a gain of 32, the internal 2.048-V reference, and a data rate of 20 SPS (see Table 1 and Table 2). Accordingly the device is able to resolve signals as small as one LSB. The LSB size is calculated using Equation 18:

To get an approximation of the achievable temperature resolution per ADC code, the LSB size is divided by the average sensitivity of a K-type thermocouple (41 µV/°C), as shown in Equation 19.

The register settings for this design are shown in Table 22.

9.2.1.3 Application Curves

Figure 75 and Figure 76 show the measurement results. The measurements are taken at T_A = T_(CJ) = 25°C. A system offset calibration is performed at T_(TC) = 25°C, which translates to a V_(TC) = 0 V when T_(CJ) = 25°C. No gain calibration is implemented. The data in Figure 75 are taken using a precision voltage source as the input signal instead of a thermocouple. The respective temperature measurement error in Figure 76 is calculated from the data in Figure 75 using the NIST tables.

The design meets the required temperature measurement accuracy given in Table 21. Note that the measurement error shown in Figure 76 does not include the error of the thermocouple itself and the measurement error of the cold-junction temperature. Those two error sources are in general larger than 0.2°C and therefore, in many cases, dominate the overall system measurement accuracy.

Figure 75. Voltage Measurement Error vs V_(TC)

Figure 76. Temperature Measurement Error vs T_(TC)

9.2.2.1 Design Requirements

9.2.2.2 Detailed Design Procedure

The circuit in Figure 77 employs a ratiometric measurement approach. In other words, the sensor signal (that is, the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out because these errors are common to both the sensor signal and the reference.

In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision, low-drift reference resistor, R_REF. The voltage, V_ref, generated across the reference resistor (as shown in Equation 20) is used as the ADC reference voltage. Equation 20 reduces to Equation 21 because I_IDAC1 = I_IDAC2.

To simplify the following discussion, the individual lead resistance values of the RTD (R_LEADx) are set to zero. Only IDAC1 excites the RTD to produce a voltage (V_RTD) proportional to the temperature-dependable RTD value and the IDAC1 value, as shown in Equation 22.

The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage against the reference voltage to produce a digital output code proportional to Equation 23 through Equation 25:

As can be seen from Equation 25, the output code only depends on the value of the RTD, the PGA gain, and the reference resistor (R_REF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current therefore does not matter. However, because the value of the reference resistor directly affects the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced by the temperature drift of R_REF.

The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance. Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, the differential voltage (V_IN) across the ADC inputs, AIN0 and AIN1, is calculated using Equation 26:

When R_LEAD1 = R_LEAD2 and I_IDAC1 = I_IDAC2, Equation 26 reduces to Equation 27:

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are well matched.

A first-order differential and common-mode RC filter (R_F1, R_F2, C_DIF1, C_CM1, and C_CM2) is placed on the ADC inputs, as well as on the reference inputs (R_F3, R_F4, C_DIF2, C_CM3, and C_CM4). The same guidelines for designing the input filter apply as described in the Thermocouple Measurement section. For best performance, TI recommends matching the corner frequencies of the input and reference filter. More detailed information on matching the input and reference filter can be found in application report RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 (SBAA201).

The reference resistor R_REF not only serves to generate the reference voltage for the device, but also sets the common-mode voltage of the RTD to within the specified common-mode voltage range of the PGA.

When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs. The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal or less than AVDD – 0.9 V in order to operate accurately. This requirement means that Equation 28 must be met at all times.

The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter resistor values R_F1 and R_F2 are small enough and well matched, IDAC1 can be routed to AIN1 and IDAC2 to AIN0 in Figure 77. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured with a single device.

This design example discusses the implementation of a 3-wire Pt100 measurement to be used to measure temperatures ranging from –200°C to +850°C as stated in Table 23. The excitation current for the Pt100 is chosen as I_IDAC1 = 500 µA, which means a combined current of 1 mA is flowing through the reference resistor, R_REF. As mentioned previously, besides creating the reference voltage for the ADS1120, the voltage across R_REF also sets the common-mode voltage for the RTD measurement. In general, choose the largest reference voltage possible while still maintaining the compliance voltage of the IDACs as well as meeting the common-mode voltage requirement of the PGA. TI recommends setting the common-mode voltage at or near half the analog supply (in this case 3.3 V / 2 = 1.65 V), which in most cases satisfies the common-mode voltage requirements of the PGA. The value for R_REF is then calculated by Equation 29:

The stability of R_REF is critical to achieve good measurement accuracy over temperature and time. Choosing a reference resistor with a temperature coefficient of ±10 ppm/°C or better is advisable. If a 1.65 kΩ value is not readily available, another value near 1.65 kΩ (such as 1.62 kΩ or 1.69 kΩ) can certainly be used as well.

As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured (V_{IN (MAX)}) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of approximately 391 Ω as per the NIST tables. The voltage across the Pt100 equates to Equation 30:

The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV) = 8.4. The next smaller PGA gain setting available in the ADS1120 is 8. At a gain of 8, the ADS1120 offers a FSR value as described in Equation 31:

This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.

After selecting the values for the IDACs, R_REF, and PGA gain, make sure to double check that the settings meet the common-mode voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the true common-mode voltage at the ADC inputs (AIN0 and AIN1) the lead resistance must be taken into account as well.

The smallest common-mode voltage occurs at the lowest measurement temperature (–200°C) with R_LEADx = 0 Ω and is calculated using Equation 32 and Equation 33.

Actually, assuming V_{CM (MIN)} = V_ref is a sufficient approximation.

V_{CM (MIN)} must meet two requirements: Equation 15 requires V_{CM (MIN)} to be larger than AVDD / 4 = 3.3 V / 4 = 0.825 V and Equation 13 requires V_{CM (MIN)} to meet Equation 34:

Both restrictions are satisfied in this design with a V_{CM (MIN)} = 1.65 V.

The largest common-mode voltage occurs at the highest measurement temperature (850°C) and is calculated using Equation 35 and Equation 36.

V_{CM (MAX)} does meet the requirement given by Equation 14, which in this design equates to Equation 37:

Finally, the maximum voltage that can occur on input AIN1 must be calculated to determine if the compliance voltage (AVDD – 0.9 V = 3.3 V – 0.9 V = 2.4 V) of IDAC1 is met. Note that the voltage on input AIN0 is smaller than the one on input AIN1. Equation 38 and Equation 39 show that the voltage on AIN1 is less than 2.4 V, even when taking the worst-case lead resistance into account.

The register settings for this design are shown in Table 24.

9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements

Implementing a 2- or 4-wire RTD measurement is very similar to the 3-wire RTD measurement illustrated in Figure 77, except that only one IDAC is required.

Figure 78 shows a typical circuit implementation of a 2-wire RTD measurement. The main difference compared to a 3-wire RTD measurement is with respect to the lead resistance compensation. The voltage drop across the lead resistors, R_LEAD1 and R_LEAD2, in this configuration is directly part of the measurement (as shown in Equation 40) because there is no means to compensate the lead resistance by use of the second current source. Any compensation must be done by calibration.

Equation 40. V_IN = I_IDAC1 · (R_LEAD1 + R_RTD + R_LEAD2)

Figure 78. 2-Wire RTD Measurement

Figure 79 shows a typical circuit implementation of a 4-wire RTD measurement. Similar to the 2-wire RTD measurement, only one IDAC is required for exciting and measuring a 4-wire RTD in a ratiometric manner. The main benefit of using a 4-wire RTD is that the ADC inputs are connected to the RTD in the form of a Kelvin connection. Apart from the input leakage currents of the ADC, there is no current flow through the lead resistors R_LEAD2 and R_LEAD3 and therefore no voltage drop is created across them. The voltage at the ADC inputs consequently equals the voltage across the RTD and the lead resistance is of no concern.

Figure 79. 4-Wire RTD Measurement

Note that because only one IDAC is used and flows through the reference resistor, R_REF, the transfer function of a 2- and 4-wire RTD measurement differs compared to the one of a 3-wire RTD measurement by a factor of 2, as shown in Equation 41.

Equation 41. Code ∝ (R_{RTD (at Temperature)} · Gain) / R_REF

In addition, the common-mode and reference voltage is reduced compared to the 3-wire RTD configuration. Therefore, some further modifications may be required in case the 3-wire RTD design is used to measure 2- and 4-wire RTDs as well. If the decreased common-mode voltage does not meet the V_{CM (MIN)} requirements of the PGA anymore, either increase the value of R_REF by switching in a larger resistor or, alternatively, increase the excitation current while decreasing the gain at the same time.

9.2.2.3 Application Curves

Figure 80 and Figure 81 show the measurement results. The measurements are taken at T_A = 25°C. A system offset calibration is performed using a reference resistor of 100 Ω. No gain calibration is implemented. The data in Figure 80 are taken using precision resistors instead of a 3-wire Pt100. The respective temperature measurement error in Figure 81 is calculated from the data in Figure 80 using the NIST tables.

The design meets the required temperature measurement accuracy given in Table 23. Note that the measurement error shown in Figure 81 does not include the error of the RTD itself.

Figure 80. Resistance Measurement Error vs R_RTD

Figure 81. Temperature Measurement Error vs T_(RTD)

9.2.3.1 Design Requirements

9.2.3.2 Detailed Design Procedure

To implement a ratiometric bridge measurement, the bridge excitation voltage is simultaneously used as the reference voltage for the ADC; see Figure 82. With this configuration, any drift in excitation voltage also shows up on the reference voltage, consequently canceling out drift error. Either of the two device reference input pairs can be connected to the bridge excitation voltage. However, only the negative reference input (REFN1) can be internally routed to a low-side power switch. By connecting the low side of the bridge to REFN1, the device can automatically power-down the bridge by opening the low-side power switch. When the PSW bit in the configuration register is set to 1, the device opens the switch every time a POWERDOWN command is issued and closes the switch again when a START/SYNC command is sent.

The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal use of the ADC full-scale range. Using a symmetrical bridge with the excitation voltage equal to the supply voltage of the device ensures that the output signal of the bridge meets the common-mode voltage requirement of the PGA.

Note that the maximum input voltage of ADS1120 is limited to V_{IN (MAX)} = ±[(AVDD – AVSS) – 0.4 V] / Gain, which means the entire full-scale range, FSR = ±(AVDD – AVSS) / Gain, cannot be used in this configuration. This limitation is a result of the output drive capability of the PGA amplifiers (A1 and A2); see Figure 39. The output of each amplifier must stay 200 mV away from the rails (AVDD and AVSS), otherwise the PGA becomes nonlinear. Consequently, the maximum output swing of the PGA is limited to V_OUT = ±[(AVDD – AVSS) – 0.4 V].

Using a 2-mV/V load cell with a 5-V excitation yields a maximum differential output voltage of V_{IN (MAX)} = ±10 mV, which meets Equation 42 when using a gain of 128.

A first-order differential and common-mode RC filter (R_F1, R_F2, C_DIF1, C_CM1, and C_CM2) is placed on the ADC inputs. The reference has an additional capacitor C_DIF2 to limit reference noise. Care must be taken to maintain a limited amount of filtering or the measurement will no longer be ratiometric.

The device is capable of 16-bit, noise-free resolution using a gain of 128 at 20 SPS for the specified reference voltage. Accordingly the device is able to resolve signals as small as one LSB. The LSB size is calculated using Equation 43:

To find the total number of counts available for the bridge measurement, the maximum output voltage is divided by the LSB value. Dividing 10 mV by 1.192 µV equates to 8389 total counts available, which meets the design parameter of 8000 counts.

The register settings for this design are shown in Table 26.