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  • ADS114x 16-Bit, 2-kSPS, Analog-to-Digital Converters With Programmable Gain Amplifier (PGA) for Sensor Measurement

    • SBAS453G July   2009  – August 2016 ADS1146 , ADS1147 , ADS1148

      PRODUCTION DATA.  

  • CONTENTS
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  • ADS114x 16-Bit, 2-kSPS, Analog-to-Digital Converters With Programmable Gain Amplifier (PGA) for Sensor Measurement
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  ADC Input and Multiplexer
      2. 9.3.2  Low-Noise PGA
        1. 9.3.2.1 PGA Common-Mode Voltage Requirements
        2. 9.3.2.2 PGA Common-Mode Voltage Calculation Example
        3. 9.3.2.3 Analog Input Impedance
      3. 9.3.3  Clock Source
      4. 9.3.4  Modulator
      5. 9.3.5  Digital Filter
      6. 9.3.6  Voltage Reference Input
      7. 9.3.7  Internal Voltage Reference
      8. 9.3.8  Excitation Current Sources
      9. 9.3.9  Sensor Detection
      10. 9.3.10 Bias Voltage Generation
      11. 9.3.11 General-Purpose Digital I/O
      12. 9.3.12 System Monitor
        1. 9.3.12.1 Power-Supply Monitor
        2. 9.3.12.2 External Voltage Reference Monitor
        3. 9.3.12.3 Ambient Temperature Monitor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Up
      2. 9.4.2 Reset
      3. 9.4.3 Power-Down Mode
      4. 9.4.4 Conversion Control
        1. 9.4.4.1 Settling Time for Channel Multiplexing
        2. 9.4.4.2 Channel Cycling and Overload Recovery
        3. 9.4.4.3 Single-Cycle Settling
        4. 9.4.4.4 Digital Filter Reset Operation
      5. 9.4.5 Calibration
        1. 9.4.5.1 Offset Calibration Register: OFC[2:0]
        2. 9.4.5.2 Full-Scale Calibration Register: FSC[2:0]
        3. 9.4.5.3 Calibration Commands
          1. 9.4.5.3.1 System Offset and Self Offset Calibration
          2. 9.4.5.3.2 System Gain Calibration
        4. 9.4.5.4 Calibration Timing
    5. 9.5 Programming
      1. 9.5.1 Digital Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Ready (DRDY)
        5. 9.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 9.5.1.6 SPI Reset
        7. 9.5.1.7 SPI Communication During Power-Down Mode
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  WAKEUP (0000 000x)
        2. 9.5.3.2  SLEEP (0000 001x)
        3. 9.5.3.3  SYNC (0000 010x)
        4. 9.5.3.4  RESET (0000 011x)
        5. 9.5.3.5  RDATA (0001 001x)
        6. 9.5.3.6  RDATAC (0001 010x)
        7. 9.5.3.7  SDATAC (0001 011x)
        8. 9.5.3.8  RREG (0010 rrrr, 0000 nnnn)
        9. 9.5.3.9  WREG (0100 rrrr, 0000 nnnn)
        10. 9.5.3.10 SYSOCAL (0110 0000)
        11. 9.5.3.11 SYSGCAL (0110 0001)
        12. 9.5.3.12 SELFOCAL (0110 0010)
        13. 9.5.3.13 NOP (1111 1111)
        14. 9.5.3.14 Restricted Command (1111 0001)
    6. 9.6 Register Maps
      1. 9.6.1 ADS1146 Register Map
      2. 9.6.2 ADS1146 Detailed Register Definitions
        1. 9.6.2.1 BCS—Burn-out Current Source Register (offset = 00h) [reset = 01h]
        2. 9.6.2.2 VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.2.3 MUX—Multiplexer Control Register (offset = 02h) [reset = x0h]
        4. 9.6.2.4 SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.2.5 OFC—Offset Calibration Coefficient Registers (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.2.6 FSC—Full-Scale Calibration Coefficient Registers (offset = 07h, 08h, 09h) [reset = 00h, 00h, 40h]
        7. 9.6.2.7 ID—ID Register (offset = 0Ah) [reset = x0h]
      3. 9.6.3 ADS1147 and ADS1148 Register Map
      4. 9.6.4 ADS1147 and ADS1148 Detailed Register Definitions
        1. 9.6.4.1  MUX0—Multiplexer Control Register 0 (offset = 00h) [reset = 01h]
        2. 9.6.4.2  VBIAS—Bias Voltage Register (offset = 01h) [reset = 00h]
        3. 9.6.4.3  MUX1—Multiplexer Control Register 1 (offset = 02h) [reset = x0h]
        4. 9.6.4.4  SYS0—System Control Register 0 (offset = 03h) [reset = 00h]
        5. 9.6.4.5  OFC—Offset Calibration Coefficient Register (offset = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 9.6.4.6  FSC—Full-Scale Calibration Coefficient Register (offset = 07h, 08h, 09h) [reset = 00h, 00h, 40h]
        7. 9.6.4.7  IDAC0—IDAC Control Register 0 (offset = 0Ah) [reset = x0h]
        8. 9.6.4.8  IDAC1—IDAC Control Register 1 (offset = 0Bh) [reset = FFh]
        9. 9.6.4.9  GPIOCFG—GPIO Configuration Register (offset = 0Ch) [reset = 00h]
        10. 9.6.4.10 GPIODIR—GPIO Direction Register (offset = 0Dh) [reset = 00h]
        11. 9.6.4.11 GPIODAT—GPIO Data Register (offset = 0Eh) [reset = 00h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
      8. 10.1.8 Channel Multiplexing Example
      9. 10.1.9 Power-Down Mode Example
    2. 10.2 Typical Applications
      1. 10.2.1 Ratiometric 3-Wire RTD Measurement System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Topology
          2. 10.2.1.2.2 RTD Selection
          3. 10.2.1.2.3 Excitation Current
          4. 10.2.1.2.4 Reference Resistor, RREF
          5. 10.2.1.2.5 PGA Setting
          6. 10.2.1.2.6 Common-Mode Input Range
          7. 10.2.1.2.7 Input and Reference Low-Pass Filters
          8. 10.2.1.2.8 Register Settings
        3. 10.2.1.3 Application Curves
      2. 10.2.2 K-Type Thermocouple Measurement (-200°C to 1250°C) With Cold-Junction Compensation
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Biasing Resistors
          2. 10.2.2.2.2 Input Filtering
          3. 10.2.2.2.3 PGA Setting
          4. 10.2.2.2.4 Cold-Junction Measurement
          5. 10.2.2.2.5 Calculated Resolution
          6. 10.2.2.2.6 Register Settings
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Power Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PW|16
    • MPDS361A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sbas453g_oa
  • sbas453g_pm
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DATA SHEET

ADS114x 16-Bit, 2-kSPS, Analog-to-Digital Converters With Programmable Gain Amplifier (PGA) for Sensor Measurement

1 Features

  • Programmable Data Rates Up to 2 kSPS
  • Single-Cycle Settling for All Data Rates
  • Simultaneous 50-Hz and 60-Hz Rejection at
    20 SPS
  • Analog Multiplexer With 8 (ADS1148) and
    4 (ADS1147) Independently Selectable Inputs
  • Programmable Gain: 1 V/V to 128 V/V
  • Dual-Matched Programmable Excitation Current Sources
  • Low-Drift Internal 2.048-V Reference
  • Sensor Burnout Detection
  • 4 or 8 General-Purpose I/Os (ADS1147 and ADS1148)
  • Internal Temperature Sensor
  • Power Supply and VREF Monitoring (ADS1147 and ADS1148)
  • Self and System Calibration
  • SPI™-Compatible Serial Interface
  • Analog Supply: Unipolar (2.7 V to 5.25 V) or Bipolar (±2.5 V)
  • Digital Supply: 2.7 V to 5.25 V

2 Applications

  • Temperature Measurement
    • RTDs, Thermocouples, and Thermistors
  • Pressure Measurement
  • Flow Meters
  • Factory Automation and Process Control

3 Description

The ADS1146, ADS1147, and ADS1148 devices are precision, 16-bit analog-to-digital converters (ADCs) that include many integrated features to reduce system cost and component count for sensor measurement applications. The devices feature a low-noise, programmable gain amplifier (PGA), a precision delta-sigma (ΔΣ) ADC with a single-cycle settling digital filter, and an internal oscillator. The ADS1147 and ADS1148 devices also provide a built-in, low-drift voltage reference, and two matched programmable excitation current sources (IDACs).

An input multiplexer supports four differential inputs for the ADS1148, two for the ADS1147, and one for the ADS1146. In addition, the multiplexer integrates sensor burn-out detection, voltage bias for thermocouples, system monitoring, and general purpose digital I/Os (ADS1147 and ADS1148). The PGA provides selectable gains up to 128 V/V. These features provide a complete front-end solution for temperature sensor measurement applications including thermocouples, thermistors, and resistance temperature detectors (RTDs) and other small signal measurements including resistive bridge sensors. The digital filter settles in a single cycle to support fast channel cycling when using the input multiplexer and provides data rates up to 2 kSPS. For data rates of 20 SPS or less, both 50-Hz and 60-Hz interference are rejected by the filter.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS1146 TSSOP (16) 5.00 mm × 4.40 mm
ADS1147 TSSOP (20) 6.50 mm × 4.40 mm
ADS1148 TSSOP (28) 9.70 mm × 4.40 mm
VQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Functional Block Diagrams

ADS1146 ADS1147 ADS1148 ai_46_47_48_fbd_new_sbas453.gif

4 Revision History

Changes from F Revision (April 2012) to G Revision

  • Added ESD Ratings table and Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sectionsGo
  • Updated Features and Description sections to include use in applications other than temperature measurementGo
  • Merged all Pin Functions into one tableGo
  • Changed values in the Thermal Information table to align with JEDEC standardsGo
  • Added Absolute input current specification to Electrical CharacteristicsGo
  • Changed compliance voltage for excitation current sources in Electrical Characteristics, now refers to Figure 9 and Figure 10; changed initial error and initial mismatch to absolute error and absolute mismatchGo
  • Changed IDAC mismatch specification in Electrical Characteristics table to reflect proper distributionGo
  • Re-ordered elements in Timing Requirements tables, changed timing references to tCLKGo
  • Changed Low-Noise PGA sectionGo
  • Modified Figure 20 to show variable resistor position Go
  • Added fCLK/fMOD column to Table 5Go
  • Changed Chip Select (CS) sectionGo
  • Changed Data Output and Data Ready (DOUT/DRDY) sectionGo
  • Changed Figure 42, 43, and 44Go
  • Added more infomation to Data Format section; added Figure 45Go
  • Modified Figure 46 to include CS status through SLEEP and WAKEUP commandGo
  • Updated Figure 47 and Figure 48 to show start of command executionGo
  • Removed figure for SDATAC (0001 011x) (Stop Read Data Continuous) commandGo
  • Updated Figure 53 to show MUX1 as the start of the data byte for the given command and register locationGo
  • Updated Figure 54 to show start of calibration timingGo
  • Updated Figure 79 and Figure 80 to better show timing informationGo

Changes from E Revision (April 2012) to F Revision

  • Added ADS1148, QFN-32 row to Package/Ordering Information tableGo

Changes from D Revision (October 2011) to E Revision

  • Added RHB pin configurationGo

Changes from C Revision (April 2010) to D Revision

  • Added footnote to Analog Inputs, Full-scale input voltage parameter typical specification in Electrical Characteristics tableGo
  • Deleted Analog Inputs, Mux leakage current parameter from Electrical Characteristics tableGo
  • Added tCSPW to minimum specification in Timing Characteristics for Figure 1Go
  • Changed tDTS minimum specification in Timing RequirementsGo
  • Updated Figure 1 to show tCSPW timingGo
  • Added Figure 6, Figure 5, Figure 9, and Figure 10Go
  • Added Figure 15, Figure 16, Figure 11, and Figure 12Go
  • Corrected Figure 19 to remove constant shortGo
  • Added Table 4 to Analog Input Impedance sectionGo
  • Corrected Figure 29 and Figure 30Go
  • Added details to Bias Voltage Generation sectionGo
  • Added Channel Cycling and Overload Recovery sectionGo
  • Corrected Table 10Go
  • Added Equation 18 to Calibration sectionGo
  • Added details to Calibration Commands sectionGo
  • Added details to Digital Interface sectionGo
  • Added Restricted command to Table 15Go

5 Device Comparison Table

PRODUCT RESOLUTION (BITS) NUMBER OF INPUTS VOLTAGE REFERENCE EXCITATION CURRENT SOURCES PACKAGE (PINS)
ADS1246 24 1 Differential External No TSSOP (16)
ADS1247 24 4-Input Multiplexer Internal or External Yes TSSOP (20)
ADS1248 24 8-Input Multiplexer Internal or External Yes TSSOP (28)
ADS1146 16 1 Differential External No TSSOP (16)
ADS1147 16 4-Input Multiplexer Internal or External Yes TSSOP (20)
ADS1148 16 8-Input Multiplexer Internal or External Yes TSSOP (28)
16 8-Input Multiplexer Internal or External Yes VQFN (32)

6 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
PW Package
20-Pin TSSOP
Top View
PW Package
28-Pin TSSOP
Top View
RHB Package
32-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION(2)
NAME ADS1146 ADS1147 ADS1148
TSSOP (16) TSSOP (20) TSSOP (28) VQFN (32)
AIN0/IEXC — 9 11 17 I Analog input 0, optional excitation current output
AIN1/IEXC — 10 12 18 I Analog input 1, optional excitation current output
AIN2/IEXC/GPIO2 — 11 17 23 I/O Analog input 2, optional excitation current output,
or general-purpose digital input/output pin 2
AIN3/IEXC/GPIO3 — 12 18 24 I/O Analog input 3, optional excitation current output,
or general-purpose digital input/output pin 3
AIN4/IEXC/GPIO4 — — 13 19 I/O Analog input 4, optional excitation current output,
or general-purpose digital input/output pin 4
AIN5/IEXC/GPIO5 — — 14 20 I/O Analog input 5, optional excitation current output,
or general-purpose digital input/output pin 5
AIN6/IEXC/GPIO6 — — 15 21 I/O Analog input 6, optional excitation current output,
or general-purpose digital input/output pin 6
AIN7/IEXC/GPIO7 — — 16 22 I/O Analog input 7, optional excitation current output,
or general-purpose digital input/output pin 7
AINN 8 — — — I Negative analog input
AINP 7 — — — I Positive analog input
AVDD 10 14 22 28 P Positive analog power supply, connect a 0.1-µF capacitor to AVSS
AVSS 9 13 21 27 P Negative analog power supply
CLK 3 3 3 9 I External clock input, tie to DGND to activate the internal oscillator.
CS 12 16 24 30 I Chip select (active low)
DGND 2 2 2 8 G Digital ground
DIN 15 19 27 1 I Serial data input
DOUT/DRDY 14 18 26 32 O Serial data output, or data out combined with data ready
DRDY 13 17 25 31 O Data ready (active low)
DVDD 1 1 1 7 P Digital power supply, connect a 0.1-µF capacitor to DGND
IEXC1 — — 20 26 O Excitation current output 1
IEXC2 — — 19 25 O Excitation current output 2
NC — — — 3, 4, 5, 6 — Connect pin to AVSS or leave floating
REFN 6 — — — I Negative external reference input
REFN0/GPIO1 — 6 6 12 I/O Negative external reference input 0,
or general-purpose digital input/output pin 1
REFN1 — — 8 14 I Negative external reference input 1
REFP 5 — — — I Positive external reference input
REFP0/GPIO0 — 5 5 11 I/O Positive external reference input 0,
or general-purpose digital input/output pin 1
REFP1 — — 7 13 I Positive external reference input 1
RESET 4 4 4 10 I Reset (active low)
SCLK 16 20 28 2 I Serial clock input
START 11 15 23 29 I Conversion start
Thermal Pad — — — 33 — Connect pin to AVSS or leave floating
VREFCOM — 8 10 16 O Negative internal reference voltage output, connect to AVSS when using a unipolar supply or to the mid-voltage ground when using a bipolar supply
VREFOUT — 7 9 15 O Positive internal reference voltage output, connect a capacitor in the range of 1 µF to 47 µF to VREFCOM
(1) G = Ground, I = Input, O = Output, P = Power
(2) See Unused Inputs and Outputs for unused pin connections.

 
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