The ADS1148-Q1 is a highly-integrated, precision, 16-bit analog-to-digital converter (ADC) that includes many integrated features to reduce system cost and component count for sensor measurement applications. The device features a low-noise, programmable gain amplifier (PGA), a precision delta-sigma (ΔΣ) ADC with a single-cycle settling digital filter, and an internal oscillator. The
ADS1148-Q1 integrates a low-drift voltage reference, and two matched programmable excitation current sources (IDACs).
The device offers a fully flexible multiplexer that allows both positive and negative inputs to be selected independently. In addition, the multiplexer integrates sensor burn-out detection, voltage bias for thermocouples, system monitoring, and eight general-purpose digital I/Os (GPIOs). The PGA provides selectable gains up to 128 V/V. These features provide a complete front-end solution for temperature sensor measurement applications, including thermocouples, thermistors, and resistance temperature detectors (RTDs), and other small-signal measurements. The digital filter settles in a single cycle to support fast channel cycling when using the input multiplexer and provides data rates up to 2 kSPS. For data rates of 20 SPS or less, both the 50-Hz and 60-Hz interference are rejected by the filter.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS1148-Q1 | TSSOP (28) | 9.70 mm × 4.40 mm |
Changes from * Revision (July 2014) to A Revision
PIN | TYPE(1) | DESCRIPTION(2) | |
---|---|---|---|
NAME | NO. | ||
AIN0/IEXC | 11 | I | Analog input 0, optional excitation current output |
AIN1/IEXC | 12 | I | Analog input 1, optional excitation current output |
AIN2/IEXC/GPIO2 | 17 | I/O | Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2 |
AIN3/IEXC/GPIO3 | 18 | I/O | Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3 |
AIN4/IEXC/GPIO4 | 13 | I/O | Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4 |
AIN5/IEXC/GPIO5 | 14 | I/O | Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5 |
AIN6/IEXC/GPIO6 | 15 | I/O | Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6 |
AIN7/IEXC/GPIO7 | 16 | I/O | Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7 |
AVDD | 22 | P | Positive analog power supply, connect a 0.1-µF capacitor to AVSS |
AVSS | 21 | P | Negative analog power supply |
CLK | 3 | I | External clock input, tie to DGND to activate the internal oscillator |
CS | 24 | I | Chip select (active low) |
DGND | 2 | G | Digital ground |
DIN | 27 | I | Serial data input |
DOUT/DRDY | 26 | O | Serial data output, or data out combined with data ready |
DRDY | 25 | O | Data ready (active low) |
DVDD | 1 | P | Digital power supply, connect a 0.1-µF capacitor to DGND |
IEXC1 | 20 | O | Excitation current output 1 |
IEXC2 | 19 | O | Excitation current output 2 |
REFN0/GPIO1 | 6 | I/O | Negative external reference input 0, or general-purpose digital input/output pin 1 |
REFN1 | 8 | I | Negative external reference input 1 |
REFP0/GPIO0 | 5 | I/O | Positive external reference input 0, or general-purpose digital input/output pin 1 |
REFP1 | 7 | I | Positive external reference input 1 |
RESET | 4 | I | Reset (active low) |
SCLK | 28 | I | Serial clock input |
START | 23 | I | Conversion start |
VREFCOM | 10 | O | Negative internal reference voltage output, connect to AVSS when using a unipolar supply or to the mid-voltage ground when using a bipolar supply |
VREFOUT | 9 | O | Positive internal reference voltage output, connect a capacitor in the range of 1 µF to 47 µF to VREFCOM |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | AVDD to AVSS | –0.3 | 5.5 | V |
AVSS to DGND | –2.8 | 0.3 | ||
DVDD to DGND | –0.3 | 5.5 | ||
Analog input voltage | AINx, REFPx, REFNx, VREFOUT, VREFCOM, IEXC1, IEXC2 | AVSS – 0.3 | AVDD + 0.3 | V |
Digital input voltage | SCLK, DIN, DOUT/DRDY, DRDY, CS, START, RESET, CLK | DGND – 0.3 | DVDD + 0.3 | V |
Input current | Continuous, any pin except power-supply pins | –10 | 10 | mA |
Momentary, any pin except power-supply pins | –100 | 100 | ||
Temperature | Junction, TJ | 150 | °C | |
Storage, Tstg | –60 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±750 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
Analog power supply | AVDD to AVSS | 2.7 | 5.25 | V | ||
AVSS to DGND | –2.65 | 0.1 | ||||
AVDD to DGND | 2.25 | 5.25 | ||||
Digital power supply | DVDD to DGND | 2.7 | 5.25 | V | ||
ANALOG INPUTS(2) | ||||||
VIN | Differential input voltage | V(AINP) – V(AINN)(1) | –VREF / Gain | VREF / Gain | V | |
VCM | Common-mode input voltage | (V(AINP) + V(AINN)) / 2 | See Equation 3 | |||
VOLTAGE REFERENCE INPUTS(3) | ||||||
VREF | Differential reference input voltage | V(REFPx) – V(REFNx) | 0.5 | (AVDD – AVSS) – 1 | V | |
V(REFNx) | Absolute negative reference voltage | AVSS – 0.1 | V(REFPx) – 0.5 | V | ||
V(REFPx) | Absolute positive reference voltage | V(REFNx) + 0.5 | AVDD + 0.1 | V | ||
EXTERNAL CLOCK INPUT(4) | ||||||
fCLK | External clock frequency | 1 | 4.5 | MHz | ||
External clock duty cycle | 25% | 75% | ||||
GENERAL-PURPOSE INPUTS AND OUTPUTS (GPIO) | ||||||
GPIO input voltage | AVSS | AVDD | V | |||
DIGITAL INPUTS | ||||||
Digital input voltage | DGND | DVDD | V | |||
TEMPERATURE RANGE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ADS1148-Q1 | UNIT | |
---|---|---|---|
PW (TSSOP) | |||
28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 74.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 20.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 31.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 31.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||
Differential input current | 100 | pA | ||||
Absolute input current | See Table 4 | |||||
PGA | ||||||
PGA gain settings | 1, 2, 4, 8, 16, 32, 64, 128 | V/V | ||||
SYSTEM PERFORMANCE | ||||||
Resolution | No missing codes | 16 | Bits | |||
DR | Data rate | 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 | SPS | |||
ADC conversion time | Single-cycle settling | See Table 10 | ||||
INL | Integral nonlinearity | Differential input, end point fit, Gain = 1, VCM = 2.5 V |
–1 | 0.5 | 1 | LSB |
Offset error | After calibration | –1 | 1 | LSB | ||
Offset drift | Gain = 1 | 100 | nV/°C | |||
Gain = 128 | 15 | nV/°C | ||||
Gain error | Excluding VREF errors | –0.5% | 0.5% | |||
Gain drift | Gain = 1, excludes VREF drift | 1 | ppm°C | |||
Gain = 128, excludes VREF drift | –3.5 | ppm/°C | ||||
Noise | See Table 1 and Table 2 | |||||
NMRR | Normal mode rejection | See Table 6 | ||||
CMRR | Common-mode rejection ratio | At dc, gain = 1 | 90 | dB | ||
At dc, gain = 32 | 100 | |||||
PSRR | Power-supply rejection ratio | AVDD, DVDD at dc | 100 | dB | ||
VOLTAGE REFERENCE INPUTS | ||||||
Reference input current | 30 | nA | ||||
INTERNAL VOLTAGE REFERENCE | ||||||
VREF | Internal reference voltage | 2.038 | 2.048 | 2.058 | V | |
Reference drift(1) | TA = –40°C to +125°C | 20 | 50 | ppm/°C | ||
Output current(2) | –10 | 10 | mA | |||
Load regulation | 50 | µV/mA | ||||
INTERNAL OSCILLATOR | ||||||
Internal oscillator frequency | 3.85 | 4.096 | 4.3 | MHz | ||
EXCITATION CURRENT SOURCES (IDACs) | ||||||
Output current settings | 50, 100, 250, 500, 750, 1000, 1500 | µA | ||||
Compliance voltage | All currents | See Figure 9 and Figure 10 | ||||
Absolute error | All currents, each IDAC | –6% | ±1% | 6% | ||
Absolute mismatch | All currents, between IDACs | ±0.2% | ||||
Temperature drift | Each IDAC | 200 | ppm/°C | |||
Temperature drift matching | Between IDACs | 10 | ppm/°C | |||
BURN-OUT CURRENT SOURCES | ||||||
Burn-out current source settings | 0.5, 2, 10 | µA | ||||
BIAS VOLTAGE | ||||||
Bias voltage | (AVDD + AVSS) / 2 | V | ||||
Bias voltage output impedance | 400 | Ω | ||||
TEMPERATURE SENSOR | ||||||
Output voltage | TA = 25°C | 118 | mV | |||
Temperature coefficient | 405 | µV/°C | ||||
GENERAL-PURPOSE INPUTS AND OUTPUTS (GPIO) | ||||||
VIL | Low-level input voltage | AVSS | 0.3 × AVDD | V | ||
VIH | High-level input voltage | 0.7 × AVDD | AVDD | V | ||
VOL | Low-level output voltage | IOL = 1 mA | AVSS | 0.2 × AVDD | V | |
VOH | High-level output voltage | IOH = 1 mA | 0.8 × AVDD | V | ||
DIGITAL INPUTS AND OUTPUTS (OTHER THAN GPIO) | ||||||
VIL | Low-level input voltage | DGND | 0.3 × DVDD | V | ||
VIH | High-level input voltage | 0.7 × DVDD | DVDD | V | ||
VOL | Low-level output voltage | IOL = 1 mA | DGND | 0.2 × DVDD | V | |
VOH | High-level output voltage | IOH = 1 mA | 0.8 × DVDD | V | ||
Input leakage | DGND < VIN < DVDD | –10 | 10 | µA | ||
POWER SUPPLY | ||||||
IAVDD | Analog supply current | Power-down mode | 0.1 | µA | ||
Converting, AVDD = 3.3 V, DR = 20 SPS, external reference |
212 | |||||
Converting, AVDD = 5 V, DR = 20 SPS, external reference |
225 | |||||
Additional current with internal reference enabled | 180 | |||||
IDVDD | Digital supply current | Power-down mode | 0.2 | µA | ||
Normal operation, DVDD = 3.3 V, DR = 20 SPS, internal oscillator |
210 | |||||
Normal operation, DVDD = 5 V, DR = 20 SPS, internal oscillator |
230 | |||||
PD | Power dissipation | AVDD = DVDD = 3.3 V, DR = 20 SPS, internal oscillator, external reference |
1.4 | mW | ||
AVDD = DVDD = 5 V, DR = 20 SPS, internal oscillator, external reference |
2.3 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
SERIAL INTERFACE (See Figure 1 and Figure 2) | |||||
tCSSC | Delay time, first SCLK rising edge after CS falling edge | 10 | ns | ||
tSCCS | Delay time, CS rising edge after final SCLK falling edge | 7 | tCLK(1) | ||
tCSPW | Pulse duration, CS high | 7 | tCLK | ||
tSCLK | SCLK period | 488 | ns | ||
64 | Conversions | ||||
tSPWH | Pulse duration, SCLK high | 0.3 | 0.7 | tSCLK | |
tSPWL | Pulse duration, SCLK low | 0.3 | 0.7 | tSCLK | |
tDIST | Setup time, DIN valid before SCLK falling edge | 25 | ns | ||
tDIHD | Hold time, DIN valid after SCLK falling edge | 25 | ns | ||
tSTD | Setup time, SCLK low before DRDY rising edge | 7 | tCLK | ||
tDTS | Delay time, SCLK rising edge after DRDY falling edge | 1 | tCLK | ||
MINIMUM START TIME PULSE DURATION (See Figure 3) | |||||
tSTART | Pulse duration, START high | 3 | tCLK | ||
RESET PULSE DURATION, SERIAL INTERFACE COMMUNICATION AFTER RESET (See Figure 4) | |||||
tRESET | Pulse duration, RESET low | 4 | tCLK | ||
tRHSC | Delay time, SCLK rising edge (start of serial interface communication) after RESET rising edge | 0.6(2) | ms |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tDOPD | Propagation delay time, SCLK rising edge to valid new DOUT |
DVDD ≤ 3.6 V | 50 | ns | ||
DVDD > 3.6 V | 180 | |||||
tDOHD | DOUT hold time | 0 | ns | |||
tCSDO | Propagation delay time, CS rising edge to DOUT high impedance |
25 | ns | |||
tPWH | Pulse duration, DRDY high | 3 | tCLK |
32 units |
IDAC current settings |
AVDD = 5 V |
AVDD = 3.3 V |
1.5-mA setting, 10 units |
DVDD = 5 V |
DVDD = 3.3 V |
The ADC noise performance is optimized by adjusting the data rate and PGA setting. Generally, the lowest input-referred noise is achieved using the highest gain possible, consistent with the input signal range. Do not set the gain too high or the result is an ADC overrange. Noise also depends on the output data rate. When the data rate reduces, the ADC bandwidth correspondingly reduces. This reduction in total bandwidth results in lower overall noise. Table 1 and Table 2 summarize the noise performance of the device. The data are representative of typical noise performance at TA = 25°C. The data shown are the result of averaging the readings from multiple devices and were measured with the inputs shorted together.
Table 1 lists the input-referred noise in units of µVPP for the conditions shown. Table 2 lists the corresponding data in units of effective number of bits (ENOB), where ENOB for the peak-to-peak noise is defined in Equation 1.
where
DATA RATE (SPS) |
PGA SETTING | |||||||
---|---|---|---|---|---|---|---|---|
1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | |
5 | 62.5(1) | 31.25(1) | 15.63(1) | 7.81(1) | 3.91(1) | 1.95(1) | 0.98(1) | 0.49(1) |
10 | 62.5(1) | 31.25(1) | 15.63(1) | 7.81(1) | 3.91(1) | 1.95(1) | 0.98(1) | 0.49(1) |
20 | 62.5(1) | 31.25(1) | 15.63(1) | 7.81(1) | 3.91(1) | 1.95(1) | 0.98(1) | 0.55 |
40 | 62.5(1) | 31.25(1) | 15.63(1) | 7.81(1) | 3.91(1) | 1.95(1) | 0.98(1) | 0.75 |
80 | 62.5(1) | 31.25(1) | 15.63(1) | 7.81(1) | 3.91(1) | 1.95(1) | 1.09 | 0.98 |
160 | 62.5(1) | 31.25(1) | 15.63(1) | 7.81(1) | 3.91(1) | 1.95(1) | 1.88 | 1.57 |
320 | 62.5(1) | 35.3 | 17.52 | 8.86 | 4.35 | 3.03 | 2.44 | 2.34 |
640 | 93.06 | 45.2 | 18.73 | 12.97 | 6.51 | 4.2 | 3.69 | 3.5 |
1000 | 284.59 | 129.77 | 61.3 | 33.04 | 16.82 | 9.08 | 5.42 | 4.65 |
2000 | 273.39 | 130.68 | 67.13 | 36.16 | 19.22 | 9.87 | 6.93 | 6.48 |
DATA RATE (SPS) |
PGA SETTING | |||||||
---|---|---|---|---|---|---|---|---|
1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | |
5 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
10 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
20 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 15.8 |
40 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 15.4 |
80 | 16 | 16 | 16 | 16 | 16 | 16 | 15.8 | 15 |
160 | 16 | 16 | 16 | 16 | 16 | 16 | 15.1 | 14.3 |
320 | 16 | 15.8 | 15.8 | 15.8 | 15.8 | 15.4 | 14.7 | 13.7 |
640 | 15.4 | 15.5 | 15.7 | 15.3 | 15.3 | 14.9 | 14.1 | 13.2 |
1000 | 13.8 | 13.9 | 14 | 13.9 | 13.9 | 13.8 | 13.5 | 12.7 |
2000 | 13.9 | 13.9 | 13.9 | 13.8 | 13.7 | 13.7 | 13.2 | 12.3 |
The ADS1148-Q1 includes a low-noise, high-input impedance programmable gain amplifier (PGA), a delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an adjustable single-cycle settling digital filter, an internal oscillator, and an SPI-compatible serial interface.
The ADS1148-Q1 also includes a flexible input multiplexer with system monitoring capability and general-purpose I/O settings, a low-drift voltage reference, and two matched current sources for sensor excitation. The Functional Block Diagram section shows the various functions incorporated into ADS1148-Q1.
The ADC measures the input signal through the onboard PGA. All analog inputs are connected to the internal AINP or AINN analog inputs through the analog multiplexer. Figure 17 shows a block diagram of the analog input multiplexer.
The input multiplexer connects to eight analog inputs. Any analog input pin can be selected as the positive input or negative input through the MUX0 register. The multiplexer also allows the on-chip excitation current and bias voltage to be selected to a specific channel.
Through the input multiplexer, the ambient temperature (internal temperature sensor), AVDD, DVDD, and the external reference can all be selected for measurement. See the System Monitor section for more details.
The analog inputs can also be configured as general-purpose inputs and outputs (GPIOs). See the General-Purpose Digital I/O section for more details.
ESD diodes protect the ADC inputs. To prevent these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100 mV, and do not exceed AVDD by more than 100 mV, as shown in Equation 2. Note that the same caution is true if the inputs are configured to be GPIOs.
The ADS1148-Q1 features a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 by the SYS0register. Figure 18 shows a simplified diagram of the PGA.
The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter, as shown in Figure 18. As with any PGA, ensure that the input voltage stays within the specified common-mode input range. The common-mode input (VCM) must be within the range shown in Equation 3.
Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4.
Table 3 shows the corresponding full-scale input ranges when using the internal 2.048-V reference.
PGA GAIN SETTING | FSR |
---|---|
1 | ±2.048 V |
2 | ±1.024 V |
4 | ±0.512 V |
8 | ±0.256 V |
16 | ±0.128 V |
32 | ±0.064 V |
64 | ±0.032 V |
128 | ±0.016 V |
To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.
The outputs of both amplifiers (A1 and A2) in Figure 18 cannot swing closer to the supplies (AVSS and AVDD) than 100 mV. If the outputs OUTP and OUTN are driven to within 100 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must meet Equation 5.
Translating the requirements of Equation 5 into requirements referred to the PGA inputs (AINP and AINN) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design; therefore, the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 19.
The common-mode voltage is calculated using Equation 6.
The voltages at the PGA inputs (AINP and AINN) can be expressed as Equation 7 and Equation 8.
The output voltages (V(OUTP) and V(OUTN)) can then be calculated as Equation 9 and Equation 10.
The requirements for the output voltages of amplifiers A1 and A2 (Equation 5) can now be translated into requirements for the input common-mode voltage range using Equation 9 and Equation 10, which are given in Equation 11 and Equation 12.
To calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (VIN (MAX)) that occurs in the application must be used. VIN (MAX) can be less than the maximum possible full-scale value.
The following paragraphs explain how to apply Equation 11 and Equation 12 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference of VREF = 2.5 V. The maximum possible differential input voltage VIN = (V(AINP) – V(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 11 and Equation 12 yield an allowed VCM range of 1.35 V ≤ VCM ≤ 1.95 V.
If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to VIN (MAX) = ±0.1 V, for example, then this reduced input signal amplitude relaxes the VCM restriction to 0.9 V ≤ VCM ≤ 2.4 V.
In the case of a fully differential sensor signal, each input (AINP, AINN) can swing up to ±50 mV around the common-mode voltage (V(AINP) + V(AINN)) / 2, which must remain between the limits of 0.9 V and 2.4 V. The output of a symmetrical wheatstone bridge is an example of a fully differential signal. Figure 20 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V(OUTN) is exactly at 0.1 V in this case. Any further decrease in common-mode voltage (VCM) or increase in differential input voltage (VIN) drives V(OUTN) below 0.1 V and saturates amplifier A2.
In contrast, the signal of a resistance temperature detector (RTD) is of a pseudo-differential nature (if implemented as in the 3-Wire RTD Measurement System section), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage from 0.85 V to 2.35 V. The positive input can then swing up to VIN (MAX) = 100 mV above the negative input. In this case, the common-mode voltage changes at the same time that the voltage on the positive input changes. That is, when the input signal swings between 0 V ≤ VIN ≤ VIN (MAX), the common-mode voltage swings between V(AINN) ≤ VCM ≤ V(AINN) + ½ VIN (MAX). Satisfying the common-mode voltage requirements for the maximum input voltage VIN (MAX) ensures the requirements are met throughout the entire signal range.
Figure 21 and Figure 22 show examples of both fully differential and pseudo-differential signals, respectively.
NOTE
With a unipolar power supply, the input range does not extend to the ground. Equation 11 and Equation 12 show the common-mode voltage requirements.
The device inputs are buffered through a high-input impedance PGA before reaching the ΔΣ modulator. For the majority of applications, the input current is minimal and can be neglected. However, because the PGA is chopper-stabilized for noise and offset performance, the input impedance is best described as a small absolute input current. The absolute input current for selected channels is approximately proportional to the selected modulator clock. Table 4 shows the typical values for these currents with a differential voltage coefficient and the corresponding input impedances over data rate.
CONDITION | ABSOLUTE INPUT CURRENT | EFFECTIVE INPUT IMPEDANCE |
---|---|---|
DR = 5 SPS, 10 SPS, 20 SPS | ± (0.5 nA + 0.1 nA/V) | 5000 MΩ |
DR = 40 SPS, 80 SPS, 160 SPS | ± (2 nA + 0.5 nA/V) | 1200 MΩ |
DR = 320 SPS, 640 SPS, 1 kSPS | ± (4 nA + 1 nA/V) | 600 MΩ |
DR = 2 kSPS | ± (8 nA + 2 nA/V) | 300 MΩ |
The device can use either the internal oscillator or an external clock. Connect the CLK pin to DGND before power-on or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator, with the device then operating on the external clock. After switching to the external clock, the device cannot be switched back to the internal oscillator without cycling the power supplies or resetting the device.
A third-order, delta-sigma modulator is used in the ADS1148-Q1. The modulator converts the analog input voltage into a pulse code modulated (PCM) data stream. To save power, the modulator clock runs from 32 kHz up to 512 kHz for different data rates, as shown in Table 5.
DATA RATE (SPS) |
MODULATOR RATE (fMOD)(1)
(kHz) |
fCLK / fMOD |
---|---|---|
5, 10, 20 | 32 | 128 |
40, 80, 160 | 128 | 32 |
320, 640, 1000 | 256 | 16 |
2000 | 512 | 8 |
The ADC uses linear-phase finite impulse response (FIR) digital filters that can be adjusted for different output data rates. The digital filter always settles in a single cycle.
Table 6 shows the exact data rates when an external clock equal to 4.096 MHz is used. Also shown is the signal –3-dB bandwidth, and the 50-Hz and 60-Hz attenuation. For good 50-Hz or 60-Hz rejection, use a data rate of 20 SPS or slower.
The frequency responses of the digital filter are illustrated in Figure 23 to Figure 33. Figure 26 illustrates a detailed view of the filter frequency response from 48 Hz to 62 Hz for a 20-SPS data rate. All filter plots are generated with a 4.096-MHz external clock.
Data rates and digital filter frequency responses scale proportionally with changes in the system clock frequency. The internal oscillator frequency has a variation, as specified in the Electrical Characteristics section, that also affects data rates and the digital filter frequency response.
NOMINAL DATA RATE | ACTUAL DATA RATE | –3-dB BANDWIDTH | ATTENUATION | |||
---|---|---|---|---|---|---|
fIN = 50 Hz ±0.3 Hz | fIN = 60 Hz ±0.3 Hz | fIN = 50 Hz ±1 Hz | fIN = 60 Hz ±1 Hz | |||
5 SPS | 5.018 SPS | 2.26 Hz | –106 dB | –74 dB | –81 dB | –69 dB |
10 SPS | 10.037 SPS | 4.76 Hz | –106 dB | –74 dB | –80 dB | –69 dB |
20 SPS | 20.075 SPS | 14.8 Hz | –71 dB | –74 dB | –66 dB | –68 dB |
40 SPS | 40.15 SPS | 9.03 Hz | — | — | — | — |
80 SPS | 80.301 SPS | 19.8 Hz | — | — | — | — |
160 SPS | 160.6 SPS | 118 Hz | — | — | — | — |
320 SPS | 321.608 SPS | 154 Hz | — | — | — | — |
640 SPS | 643.21 SPS | 495 Hz | — | — | — | — |
1000 SPS | 1000 SPS | 732 Hz | — | — | — | — |
2000 SPS | 2000 SPS | 1465 Hz | — | — | — | — |
The voltage reference for the device is the differential voltage between REFP and REFN, given by Equation 13.
The ADS1148-Q1 has a multiplexer that selects the reference inputs, as shown in Figure 34. The reference inputs use buffers to increase the input impedance.
As with the analog inputs, REFP0 and REFN0 can also be configured as digital I/Os.
The reference input circuit has ESD diodes to protect the inputs. To prevent the diodes from turning on, make sure the voltage on the reference input pin is not less than AVSS – 100 mV, and does not exceed AVDD + 100 mV, as shown in Equation 14.
The ADS1148-Q1 has an internal voltage reference with a low temperature coefficient. The output of the voltage reference is 2.048 V (nominal) with the capability of both sourcing and sinking up to 10 mA of current.
The voltage reference must have a capacitor connected between VREFOUT and VREFCOM. The value of the capacitance must be in the range of 1 µF to 47 µF. Large values provide more filtering of the reference; however, the turn-on time increases with capacitance, as shown in Table 7. For stability reasons, VREFCOM must have a low-impedance path to an ac ground node. VREFCOM can be connected to AVSS (for a ±2.5-V analog power supply) as long as AVSS has a low-impedance path less than 10 Ω to an ac ground. In case this impedance is higher than 10 Ω, connect a capacitor of at least 0.1 µF between VREFCOM and the ac ground node.
NOTE
Take care when the device is turned off between conversions because time is required for the voltage reference to settle to the final voltage. Allow adequate time for the internal reference to fully settle before starting a new conversion.
VREFOUT CAPACITOR | SETTLING ERROR | TIME TO REACH THE SETTLING ERROR |
---|---|---|
1 µF | ±0.5% | 70 µs |
±0.1% | 110 µs | |
4.7 µF | ±0.5% | 290 µs |
±0.1% | 375 µs | |
47 µF | ±0.5% | 2.2 ms |
±0.1% | 2.4 ms |
The internal reference is controlled by the MUX1 register; by default, the internal reference is off after power up (see the Detailed Register Definitions section for more details). Therefore, the internal reference must first be turned on and then connected through the internal reference multiplexer. The internal reference is used to generate the current reference for the excitation current sources and hence must be turned on before the excitation currents become available.
The ADS1148-Q1 provides two matched excitation current sources (IDACs) for RTD applications. For three-wire RTD applications, the matched current sources can be used to cancel the errors caused by sensor lead resistance. The output current of the IDACs can be programmed to 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, 1000 µA, or 1500 µA.
The two matched current sources can be connected to the dedicated current output pins, IEXC1 and IEXC2; see the Detailed Register Definitions section for more information. Both current sources can be connected to the same pin. The internal reference must be turned on and the proper amount of capacitance applied to VREFOUT when using the excitation current sources.
To help detect a possible sensor malfunction, the device provides selectable current sources (0.5 µA, 2 µA, or 10 µA) to function as burn-out current sources. When enabled, one current source sources current to the selected positive analog input (AINP) and the other current source sinks current from the selected negative analog input (AINN).
In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading can indicate a shorted sensor. The absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero.
The ADC readings of a functional sensor can be corrupted when the burn-out current sources are enabled. The burn-out current sources are recommended to be disabled when performing a precision measurement, and are recommended to be enabled only to test for sensor fault conditions.
A selectable bias voltage is provided for use with unbiased thermocouples. The bias voltage is (AVDD + AVSS) / 2 and can be applied to any analog input channel through the internal input multiplexer. Table 8 lists the bias voltage turn-on times for different sensor capacitances.
The internal bias voltage generator, when selected on multiple channels, causes the channels to be internally shorted. As a result, take care to limit the amount of current that can flow through the device. No more than 5 mA must be allowed to flow through this path, even if the device is in operation or powered down.
SENSOR CAPACITANCE | SETTLING TIME |
---|---|
0.1 µF | 220 µs |
1 µF | 2.2 ms |
10 µF | 22 ms |
200 µF | 450 ms |
The ADS1148-Q1 has eight pins that serve a dual purpose as either analog inputs or GPIOs.
Three registers control the function of the GPIO pins. Use the GPIO configuration register (IOCFG) to enable a pin as a GPIO pin. The GPIO direction register (IODIR) configures the GPIO pin as either an input or an output. Finally, the GPIO data register (IODAT) contains the GPIO data. If a GPIO pin is configured as an input, the respective IODAT[x] bit reads the status of the pin; if a GPIO pin is configured as an output, write the output status to the respective IODAT[x] bit. For more information about the use of GPIO pins, see the Detailed Register Definitions section.
Figure 35 shows a diagram of how these functions are combined onto a single pin. Note that when the pin is configured as a GPIO, the corresponding logic is powered from AVDD and AVSS. When the ADS1148-Q1 is operated with bipolar analog supplies, the GPIO outputs bipolar voltages. Care must be taken during loading the GPIO pins when these pins are used as outputs because large currents can cause droop or noise on the analog supplies.
The ADS1148-Q1 provides a system monitor function. This function can measure the analog power supply, digital power supply, external voltage reference, or ambient temperature. Note that the system monitor function provides a coarse result. When the system monitor is enabled, the analog inputs are disconnected.
The system monitor can measure the analog or digital power supply. When measuring the power supply (VSP), the resulting conversion is approximately 1/4 of the actual power supply voltage, as shown in Equation 15.
The ADC can measure the external voltage reference. In this configuration, the monitored external voltage reference (VREX) is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage, as shown in Equation 16.
NOTE
The internal reference voltage must be enabled when measuring an external voltage reference using the system monitor.
On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118 mV at
TA = 25°C with a temperature coefficient of 405 µV/°C.
When DVDD is powered up, the internal power-on reset module generates a pulse that resets all digital circuitry. All digital circuits are held in a reset state for 216 system clocks to allow the analog circuits and the internal digital power supply to settle. SPI communication cannot occur until the internal reset is released.
When the RESET pin goes low, the device is immediately reset. All registers are restored to default values. The device stays in reset mode as long as the RESET pin stays low. When the RESET pin goes high, the ADC comes out of reset mode and is able to convert data. After the RESET pin goes high, the digital filter and the registers are held in a reset state for 0.6 ms when fCLK = 4.096 MHz. Therefore, valid SPI communication can only be resumed 0.6 ms after the RESET pin goes high; see Figure 4. When the RESET pin goes low, the clock selection is reset to the internal oscillator.
A reset can also be performed by the RESET command through the serial interface and is functionally the same as using the RESET pin. For information about using the RESET command, see the RESET section.
Power consumption is reduced to a minimum by placing the device into power-down mode. There are two ways to put the device into power-down mode: using the SLEEP command and taking the START pin low.
During power-down mode, the internal reference status depends on the setting of the VREFCON bits in the MUX1 register; see the Register Maps section for details.
The START pin provides precise control of conversions. Pulse the START pin high to begin a conversion, as described in Figure 36 and Table 9. The conversion completion is indicated by the DRDY pin going low and with the DOUT/DRDY pin when the DRDY MODE bit is 1 in the IDAC0 register. When the conversion completes, the device automatically powers down. During power down, the conversion result can be retrieved; however, START must be taken high before communicating with the configuration registers. The device stays powered down until the START pin is returned high to begin a new conversion. When the START pin returns high, the decimation filter is held in a reset state for 32 modulator clock cycles internally to allow the analog circuits to settle.
Holding the START pin high configures the device to continuously convert; see Figure 37.
PARAMETER | DATA RATE (SPS) | VALUE | UNIT | |
---|---|---|---|---|
tCONV | Time from START pulse to DRDY and DOUT/DRDY going low | 5 | 200.295 | ms |
10 | 100.644 | ms | ||
20 | 50.825 | ms | ||
40 | 25.169 | ms | ||
80 | 12.716 | ms | ||
160 | 6.489 | ms | ||
320 | 3.247 | ms | ||
640 | 1.692 | ms | ||
1000 | 1.138 | ms | ||
2000 | 0.575 | ms |
NOTE:
SCLK is held low in this example.With the START pin held high, the ADC converts the selected input channels continuously. This configuration continues until the START pin is taken low. The START pin can also be used to perform synchronized measurements for multichannel applications by pulsing the START pin. With multiple devices, if each device receives the START pin pulse at the same time, all devices start a conversion when the START pin rises. If all devices are operating with the same data rate, all devices complete the conversion at the same time.
Conversions can also be initiated through SPI commands. Similar to using the START pin, the device can be put into a power-down mode using the SLEEP command. Functionally, this mode is similar to taking the START pin low. To initiate a conversion, the WAKEUP command powers up the ADC and starts a conversion, similar to returning the START pin high. Note that the START pin must be held high to use commands to control conversions. Do not combine using the START pin and using commands to control conversions.
Furthermore, sending a SYNC command immediately starts a new ADC conversion. For the SYNC command, the digital filter is reset, starting a new conversion without completing the previous conversion. This process is useful in synchronizing conversions from multiple devices or for maintaining periodic timing from multiple channels.
Similarly, writing to any of the first four registers (MUX0, VBIAS, MUX1, or SYS0; addresses 00h to 04h) automatically resets the digital filter. A change in any of these registers makes the appropriate setup change in the device, but also restarts the conversion similar to a SYNC command.
The device is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use, provided that the input signal has settled to the final result. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 10 for specific values.
When cycling through channels, take care when configuring the device to ensure that settling occurs within one cycle. For setups that cycle through MUX channels, but do not change PGA and data rate settings, changing the MUX0 register is sufficient. However, when changing PGA and data rate settings, ensure that an overload condition cannot occur during the data transmission. When configuration register data are transferred to the device, new settings become active at the end of each byte sent. Therefore, a brief overload condition can occur during the transmission of configuration data after the completion of the MUX0 byte and before the completion of the SYS0 byte. This temporary overload can result in intermittent incorrect readings. To ensure that an overload does not occur, the communication may need to be split into two separate communications, thus allowing the SYS0 register to before the change of the MUX0 register.
In the event of an overloaded state, take care to ensure single-cycle settling into the next cycle. Changing data rates during an overload state can cause the chopper to become unstable because the device implements a chopper-stabilized PGA. This instability results in slow settling time. To prevent this slow settling, always change the PGA setting or MUX setting to a non-overloaded state before changing the data rate.
The ADS1148-Q1 is capable of single-cycle settling across all gains and data rates. However, to achieve single-cycle settling at 2 kSPS, special care must be taken with respect to the interface using WREG to change a configuration register. When operating at 2 kSPS, the SCLK period must not exceed 520 ns, and the time between beginning to write a register byte data and the beginning of a subsequent register byte data must not exceed 4.2 µs. Additionally, when performing multiple individual write commands to the first four registers, wait at least 64 oscillator clocks before initiating another write command.
Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or when the START pin is taken high.
The filter is reset four system clocks (tCLK) after the falling edge of the seventh SCLK of the SYNC command. Similarly, if any write operation takes place in the MUX0 register, regardless of whether the register value changed or not, the filter is reset after the completion of the MUX0 write.
If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, regardless of whether the register value changed or not, the filter is reset. The reset pulse lasts for 32 modulator clocks after the completion of the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action.
Table 10 lists the conversion time after a filter reset. Note that this time depends on the operation initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions.
NOMINAL DATA RATE (SPS) | EXACT DATA RATE (SPS) |
FIRST DATA CONVERSION TIME AFTER FILTER RESET | SECOND AND SUBSEQUENT CONVERSION TIME AFTER FILTER RESET | ||||
---|---|---|---|---|---|---|---|
SYNC COMMAND, MUX0 REGISTER WRITE | HARDWARE RESET, RESET COMMAND, START PIN HIGH, WAKEUP COMMAND, VBIAS, MUX1, OR SYS0 REGISTER WRITE | ||||||
VALUE (ms)(1) | NO. OF SYSTEM CLOCK CYCLES | VALUE (ms)(1) | NO. OF SYSTEM CLOCK CYCLES | VALUE (ms)(1) | NO. OF SYSTEM CLOCK CYCLES | ||
5 | 5.019 | 199.258 | 816160 | 200.26 | 820265 | 199.250 | 816128 |
10 | 10.038 | 99.633 | 408096 | 100.635 | 412201 | 99.625 | 408064 |
20 | 20.075 | 49.820 | 204064 | 50.822 | 208169 | 49.812 | 204032 |
40 | 40.151 | 24.920 | 102072 | 25.172 | 103106 | 24.906 | 102016 |
80 | 80.301 | 12.467 | 51064 | 12.719 | 52098 | 12.453 | 51008 |
160 | 160.602 | 6.241 | 25560 | 6.492 | 26594 | 6.226 | 25504 |
320 | 321.608 | 3.124 | 12796 | 3.250 | 13314 | 3.109 | 12736 |
640 | 643.216 | 1.569 | 6428 | 1.695 | 6946 | 1.554 | 6368 |
1000 | 1000.000 | 1.014 | 4156 | 1.141 | 4674 | 1.000 | 4096 |
2000 | 2000.000 | 0.514 | 2108 | 0.578 | 2370 | 0.500 | 2048 |
The conversion data are scaled by offset and gain registers before yielding the final output code. As shown in Figure 38, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full-scale register (FSC) to digitally scale the gain. A digital clipping circuit ensures that the output code does not exceed 16 bits. Equation 17 shows the scaling.
The values of the offset and full-scale registers are set either by writing to them directly, or are set automatically by calibration commands.
The offset and gain calibration features are intended for the correction of minor system-level offset and gain errors. When entering manual values into the calibration registers, take care to avoid scaling down the gain register to values far below a scaling factor of 1.0. Under extreme situations, overranging the ADC is possible. Avoid encountering situations where analog inputs are connected to voltages greater than VREF / Gain.
Take care when increasing digital gain with the FSC register. When implementing custom digital gains less than 20% higher than nominal and offsets less than 40% of full scale, no special care is required. When operating at digital gains greater than 20% higher than nominal and offsets greater than 40% of full-scale, make sure that the offset and gain registers follow the conditions of Equation 18.
The offset calibration is a 24-bit word, composed of three 8-bit registers. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. The upper 16 bits, OFC[2:1], are the most important bits of the offset calibration register for calibration and can correct offsets ranging from –FS to +FS, as shown in Table 11. The lower eight bits, OFC[0], provide sub-LSB correction and are used by the calibration commands. If a calibration command is issued and the offset register is then read for storage and re-use later, all 24 bits of the OFC are recommended to be used. When the calibration commands are not used and the offset is corrected by writing a user-calculated value to the OFC register, only OFC[2:1] are recommended to be used and OFC[0] is recommended to be left as all zeros. A register value of 000000h provides no offset correction.
Note that although the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 11), avoid overloading the analog inputs.
OFFSET REGISTER | FINAL OUTPUT CODE WITH VIN = 0(1) |
---|---|
7FFFFFh | 8000h |
000100h | FFFFh |
000000h | 0000h |
FFFF00h | 0001h |
800000h | 7FFFh |
The full-scale or gain calibration is a 24-bit word composed of three 8-bit registers. The full-scale calibration value is 24 bits, straight binary, and normalized to 1.0 at code 400000h. Table 12 summarizes the scaling of the full-scale register. Note that although the full-scale calibration register can correct gain errors greater than 1 (with gain scaling less than 1), make sure to avoid overloading the analog inputs.
FULL-SCALE REGISTER | GAIN SCALING |
---|---|
800000h | 2 |
400000h | 1 |
200000h | 0.5 |
000000h | 0 |
The device provides commands for three types of calibration: system gain calibration, system offset calibration, and self offset calibration. Where absolute accuracy is required, a calibration is recommended to be performed after power up, a change in temperature, a change of gain, and in some cases a change in channel. At the completion of calibration the DRDY signal goes low, indicating that the calibration is complete. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the device powers down after completing calibration.
After a calibration starts, allow the calibration to complete before issuing any other commands (other than the SLEEP command). Issuing commands during a calibration can result in corrupted data. If this scenario occurs, either resend the calibration command that was aborted or issue a device reset.
System offset calibration corrects both internal and external offset errors. The system offset calibration is initiated by sending the SYSOCAL command when applying a zero differential input voltage (VIN = 0 V) to the selected analog inputs with the inputs set within the specified input common-mode range, ideally at mid-supply.
The self offset calibration is initiated by sending the SELFOCAL command. During self offset calibration, the selected inputs are disconnected from the internal circuitry and a zero differential signal is applied internally, thus connecting the inputs to mid-supply. With both offset calibrations, the offset calibration register (OFC) is updated afterwards. When either offset calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately. An offset calibration must be performed before a gain calibration.
System gain calibration corrects for gain error in the signal path. The system gain calibration is initiated by sending the SYSGCAL command when applying a full-scale input to the selected analog inputs. Afterwards, the full-scale calibration register (FSC) is updated. When a system gain calibration command is issued, the device stops the current conversion and starts the calibration procedure immediately.
When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This process provides a more accurate calibration value. The time required for calibration is shown in Table 13 and can be calculated using Equation 19.
DATA RATE (SPS) |
CALIBRATION TIME (tCAL) (ms)(1) |
---|---|
5 | 3201.01 |
10 | 1601.01 |
20 | 801.012 |
40 | 400.26 |
80 | 200.26 |
160 | 100.14 |
320 | 50.14 |
640 | 25.14 |
1000 | 16.14 |
2000 | 8.07 |
The device provides an SPI-compatible serial communication interface plus a data ready signal (DRDY). Communication is full-duplex with the exception of a few limitations in regards to the RREG command and the RDATA command. These limitations are explained in detail in the Commands section. For the basic serial interface timing characteristics, see Figure 1 and Figure 2.
The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reads and writes to the serial interface are ignored and the serial interface is reset. The DRDY pin operation is independent of CS. DRDY still indicates when a new conversion completes and is forced high in response to SCLK, even if CS is high.
Taking CS high only deactivates the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.
SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but SCLK is recommended to be kept as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and are shifted out of DOUT on the SCLK rising edge.
DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the SCLK falling edge.
The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is sent to the device when reading out data, send the no operation command (NOP) command on DIN.
The DRDY pin goes low to indicate that a new conversion is complete, and the conversion result is stored in the conversion result buffer. SCLK must be held low for tDTS after the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, do not issue commands during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted and the device is in RDATAC mode. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, DRDY is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after DRDY falls low, a short high pulse for a duration of tPWH indicates that new data are ready.
The DOUT/DRDY pin has two modes: data out (DOUT) only, or DOUT combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin and can be found in the IDAC0 register. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high.
When the DRDY MODE bit is set to 0, this pin functions as DOUT only. Data are clocked out on the SCLK rising edge, MSB first (as shown in Figure 39).
When the DRDY MODE bit is set to 1, this pin functions as both DOUT and DRDY. Data are shifted out as with DOUT, but the pin adds the DRDY function. Note that this mode is not operational when the device is in stop read data continuous mode when the SDATAC command is given.
The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected.
When the DRDY MODE bit is enabled and a new conversion is complete, DOUT/DRDY goes low. If DOUT/DRDY is already low, then this pin goes high and then goes low (as shown in Figure 40). Similar to the DRDY pin, a falling edge on the DOUT/DRDY pin signals that a new conversion result is ready. After DOUT/DRDY goes low, the data can be clocked out by providing 16 SCLKs if the device is in read data continuous mode. To force DOUT/DRDY high (so that DOUT/DRDY can be polled for a 0 instead of waiting for a falling edge), a NOP command or any other command that does not load the data output register can be sent after reading out the data. Because SCLKs can only be sent in multiples of eight, NOP can be sent to force DOUT/DRDY high if no other command is pending. The DOUT/DRDY pin goes high after the first SCLK rising edge after reading the conversion result completely (as shown in Figure 41). The same condition also applies after an RREG command. After all register bits are read out, the first SCLK rising edge forces DOUT/DRDY high. Figure 42 shows an example where sending an extra NOP command after reading out a register with an RREG command forces the DOUT/DRDY pin high.
SPI communication is reset in several ways. To reset the serial interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low resets the serial interface along with all the other digital functions. This process also returns all registers to the default values and starts a new conversion.
In systems where CS is tied low permanently, register writes must always be fully completed in 8-bit increments. If a glitch on SCLK disrupts SPI communications, commands are not recognized by the device. The device implements a timeout function for all listed commands in the Commands section in the event that data are corrupted and the CS pin is permanently tied low. The SPI timeout resets the interface if idle for 64 conversion cycles.
When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during power-down mode. Other commands do not function because the internal clock is shut down to save power during power-down mode.
The device provides 16 bits of data in binary twos complement format. The size of one code (LSB) is calculated using Equation 20.
A positive full-scale (FS) input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 14 summarizes the ideal output codes for different input signals.
INPUT SIGNAL, VIN
(AINP – AINN) |
IDEAL OUTPUT CODE(1) |
---|---|
≥ FS (215 – 1) / 215 | 7FFFh |
FS / 215 | 0001h |
0 | 0000h |
–FS / 215 | FFFFh |
≤ –FS | 8000h |
Figure 43 shows the mapping of the analog input signal to the output codes.
The device offers 13 commands to control device operation, as shown in Table 15. Some of the commands are stand-alone commands (WAKEUP, SLEEP, SYNC, RESET, SYSOCAL, SYSGCAL, and SELFOCAL). There are three additional commands used to control reading of data from the device (RDATA, RDATAC, and SDATAC). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction. A NOP command can be used to clock out data from the device without clocking in a command.
Operands:
COMMAND(1) | DESCRIPTION | 1st COMMAND BYTE | 2nd COMMAND BYTE |
---|---|---|---|
WAKEUP | Exit power down mode | 0000 000x (00h, 01h) | |
SLEEP | Enter power down mode | 0000 001x (02h, 03h) | |
SYNC | Synchronize ADC conversions | 0000 010x (04h, 05h) | 0000 010x (04,05h) |
RESET | Reset to default values | 0000 011x (06h, 07h) | |
NOP | No operation | 1111 1111 (FFh) | |
RDATA | Read data once | 0001 001x (12h, 13h) | |
RDATAC | Read data continuous mode | 0001 010x (14h, 15h) | |
SDATAC | Stop read data continuous mode | 0001 011x (16h, 17h) | |
RREG | Read from register rrrr | 0010 rrrr (2xh) | 0000 nnnn |
WREG | Write to register rrrr | 0100 rrrr (4xh) | 0000 nnnn |
SYSOCAL | System offset calibration | 0110 0000 (60h) | |
SYSGCAL | System gain calibration | 0110 0001 (61h) | |
SELFOCAL | Self offset calibration | 0110 0010 (62h) | |
Restricted | Restricted command. Never send to the device. |
1111 0001 (F1h) |
Use the WAKEUP command to power up the device after a SLEEP command. After execution of the WAKEUP command, the device powers up on the falling edge of the eighth SCLK.
The SLEEP command places the device into power-down mode. When the SLEEP command is issued, the device completes the current conversion and then goes into power-down mode. Note that this command does not automatically power down the internal voltage reference; see the VREFCON bits in the MUX1 section for each device for further details.
To exit power-down mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command.
Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device; see Figure 44.
NOTE
If the START pin is held low, a WAKEUP command does not power up the device. When using the SLEEP command, CS must be held low for the duration of the power-down mode.
The SYNC command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all devices simultaneously.
The RESET command restores the registers to the respective default values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the serial interface. If the RESET command is issued when the serial interface is out of synchronization because of a glitch on SCLK, the device does not reset. The CS pin can be used to reset the serial interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6 ms when the system clock frequency is 4.096 MHz, similar to the hardware reset. Therefore, SPI communication can only be started 0.6 ms after the RESET command is issued, as shown in Figure 46.
The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result is read out by sending 16 SCLKs, as shown in Figure 47. This command also works in RDATAC mode.
When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the serial interface, as shown in Figure 48.
The RDATAC command enables the read data continuous mode. This mode is the default mode after power-up or reset. In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion result can be received from the device after the DRDY signal goes low by sending 16 SCLKs. Reading back all the bits is not necessary, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low and the command takes effect on the next DRDY, as shown in Figure 49.
Be sure to complete data retrieval (conversion result or register read back) before DRDY returns low, otherwise the resulting data are corrupted. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs.
The SDATAC command terminates read data continuous mode. In stop read data continuous mode, the conversion result is not automatically loaded onto DOUT when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.
If DRDY is not actively monitored for data conversions, the stop read data continuous mode is the preferred method of reading data. In this mode, a read of ADC data is not interrupted by the completion of a new ADC conversion.
The RREG command outputs the data from up to 15 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the value of the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. The 2-byte command structure for RREG is listed below.
The full-duplex nature of the serial interface cannot be used when reading out register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 50. Any command sent during the readout of the register data is ignored. Thus, NOPs are recommended to be sent through DIN when reading out register data.
The WREG command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. The command structure for WREG is:
The SYSOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input common-mode range. The inputs must be near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC register is updated when the command completes. Timing for the calibration commands is shown in Figure 52.
The SYSGCAL command initiates the system gain calibration. For a system gain calibration, the input must be set to full-scale. The FSC register is updated after this operation. Timing for the calibration commands is shown in Figure 52.
The SELFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC register is updated after this operation. Timing for the calibration commands is shown in Figure 52.
This command is a no-operation command. NOP is used to clock out data without clocking in a command.
This command is a restricted command. This command must never be issued to the device.
REGISTER ADDRESS (HEX) | REGISTER NAME | REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
00h | MUX0 | BCS[1:0] | MUX_SP[2:0] | MUX_SN[2:0] | |||||
01h | VBIAS | VBIAS[7:0] | |||||||
02h | MUX1 | CLKSTAT | VREFCON[1:0] | REFSELT[1:0] | MUXCAL[2:0] | ||||
03h | SYS0 | 0 | PGA[2:0] | DR[3:0] | |||||
04h | OFC0 | OFC[7:0] | |||||||
05h | OFC1 | OFC[15:8] | |||||||
06h | OFC2 | OFC[23:16] | |||||||
07h | FSC0 | FSC[7:0] | |||||||
08h | FSC1 | FSC[15:8] | |||||||
09h | FSC2 | FSC[23:16] | |||||||
0Ah | IDAC0 | ID[3:0] | DRDY MODE | IMAG[2:0] | |||||
0Bh | IDAC1 | I1DIR[3:0] | I2DIR[3:0] | ||||||
0Ch | GPIOCFG | IOCFG[7:0] | |||||||
0Dh | GPIODIR | IODIR[7:0] | |||||||
0Eh | GPIODAT | IODAT[7:0] |
This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCS[1:0] | MUX_SP[2:0] | MUX_SN[2:0] | |||||
R/W-0h | R/W-0h | R/W-1h |
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7-6 | BCS[1:0] | R/W | 0h | Burn-out detect current source register.
These bits control the setting of the sensor burnout detect current source. 00: Burn-out current source off (default) 01: Burn-out current source on, 0.5 µA 10: Burn-out current source on, 2 µA 11: Burn-out current source on, 10 µA |
5-3 | MUX_SP[2:0] | R/W | 0h | Multiplexer selection, adc positive input.
These bits are the positive input channel selection bits. 000: AIN0 (default) 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7 |
2-0 | MUX_SN[2:0] | R/W | 1h | Multiplexer selection, adc negative input.
These bits are the negative input channel selection bits. 000: AIN0 001: AIN1 (default) 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBIAS[7:0] | |||||||
R/W-00h |
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | VBIAS[7] | R/W | 0h | VBIAS[7] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN7. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN7 |
6 | VBIAS[6] | R/W | 0h | VBIAS[6] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN6. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN6 |
5 | VBIAS[5] | R/W | 0h | VBIAS[5] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN5. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN5 |
4 | VBIAS[4] | R/W | 0h | VBIAS[4] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN4. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN4 |
3 | VBIAS[3] | R/W | 0h | VBIAS[3] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN3. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN3 |
2 | VBIAS[2] | R/W | 0h | VBIAS[2] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN2. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN2 |
1 | VBIAS[1] | R/W | 0h | VBIAS[1] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN1. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN1 |
0 | VBIAS[0] | R/W | 0h | VBIAS[0] voltage enable.
A bias voltage of mid-supply (AVDD + AVSS) / 2 is applied to AIN0. 0: Bias voltage is not enabled (default) 1: Bias voltage is applied to AIN0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKSTAT | VREFCON[1:0] | REFSELT[1:0] | MUXCAL[2:0] | ||||
R-xh | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | CLKSTAT | R | xh | Clock status.
This bit is read-only and indicates whether the internal oscillator or external clock is being used. 0: Internal oscillator in use 1: External clock in use |
6-5 | VREFCON[1:0] | R/W | 0h | Internal reference control.
These bits control the internal voltage reference. These bits allow the reference to be turned on or off completely, or allow the reference state to follow the state of the device. Note that the internal reference is required for operation of the IDAC functions. 00: Internal reference is always off (default) 01: Internal reference is always on 10, 11: Internal reference is on when a conversion is in progress and powers down when the device receives a SLEEP command or the START pin is taken low |
4-3 | REFSELT[1:0] | R/W | 0h | Reference select control.
These bits select the reference input for the ADC. 00: REFP0 and REFN0 reference inputs selected (default) 01: REFP1 and REFN1 reference inputs selected 10: Internal reference selected 11: Internal reference selected and internally connected to REFP0 and REFN0 input pins |
2-0 | MUXCAL[2:0](1) | R/W | 0h | System monitor control.
These bits are used to select a system monitor. The MUXCAL selection supercedes selections from the MUX0, MUX1, and VBIAS registers (includes MUX_SP, MUX_SN, VBIAS, and reference input selections). 000: Normal operation (default) 001: Offset calibration. The analog inputs are disconnected and AINP and AINN are internally connected to mid-supply (AVDD + AVSS) / 2. 010: Gain calibration. The analog inputs are connected to the voltage reference. 011: Temperature measurement. The inputs are connected to a diode circuit that produces a voltage proportional to the ambient temperature of the device. 100: REF1 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP1) – V(REFN1)) / 4. 101: REF0 monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (V(REFP0) – V(REFN0)) / 4. 110: Analog supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (AVDD – AVSS) / 4. 111: Digital supply monitor. The analog inputs are disconnected and AINP and AINN are internally connected to (DVDD – DGND) / 4. |
Table 20 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.
MUXCAL[2:0] | PGA GAIN SETTING | ADC INPUT |
---|---|---|
000 | Set by the SYS0 register | Normal operation |
001 | Set by the SYS0 register | Inputs shorted to mid-supply (AVDD + AVSS) / 2 |
010 | Forced to 1 | V(REFP) – V(REFN) (full-scale) |
011 | Forced to 1 | Temperature measurement diode |
100 | Forced to 1 | (V(REFP1) – V(REFN1)) / 4 |
101 | Forced to 1 | (V(REFP0) – V(REFN0)) / 4 |
110 | Forced to 1 | (AVDD – AVSS) / 4 |
111 | Forced to 1 | (DVDD – DGND) / 4 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | PGA[2:0] | DR[3:0] | |||||
R-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved.
Always write 0 |
6-4 | PGA[2:0] | R/W | 0h | Gain setting for the PGA.
These bits determine the gain of the PGA. 000: PGA = 1 (default) 001: PGA = 2 010: PGA = 4 011: PGA = 8 100: PGA = 16 101: PGA = 32 110: PGA = 64 111: PGA = 128 |
3-0 | DR[3:0] | R/W | 0h | Data output rate setting.
These bits determine the data output rate of the ADC. 0000: DR = 5 SPS (default) 0001: DR = 10 SPS 0010: DR = 20 SPS 0011: DR = 40 SPS 0100: DR = 80 SPS 0101: DR = 160 SPS 0110: DR = 320 SPS 0111: DR = 640 SPS 1000: DR = 1000 SPS 1001 to 1111: DR = 2000 SPS |
These bits make up the offset calibration coefficient register. Note that address 04h = 7-0, 05h = 15-8, and 06h = 23-16.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFC[7:0] | |||||||
R/W-00h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OFC[15:8] | |||||||
R/W-00h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
OFC[23:16] | |||||||
R/W-00h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
23-0 | OFC[23:0] | R/W | 000000h | Offset calibration register.
Three registers compose the ADC 24-bit offset calibration word and are in twos complement format. The upper 16 bits (OFC[23:8]) can correct offsets ranging from –FS to +FS, and the lower eight bits (OFC[7:0]) provide sub-LSB correction. The ADC subtracts the register value from the conversion result before full-scale operation. |
These bits make up the full-scale calibration coefficient register. Note that address 07h = 7-0, 08h = 15-8, and 09h = 23-16.
7 | 6 | 5 | 4 | 3 | 2 | 4 | 0 |
FSC[7:0] | |||||||
R/W-00h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FSC[15:8] | |||||||
R/W-00h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FSC[23:16] | |||||||
R/W-40h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
23-0 | FSC[23:0] | R/W | 400000h | Full-scale calibration register.
Three registers compose the ADC 24-bit, full-scale calibration word. The 24-bit word is straight binary. The ADC divides the register value of the FSC register by 400000h to derive the scale factor for calibration. After the offset calibration, the ADC multiplies the scale factor by the conversion result. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID[3:0] | DRDY MODE | IMAG[2:0] | |||||
R-xh | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7-4 | ID[3:0] | R | xh | Revision identification.
Read-only, factory-programmed bits used for revision identification. Note: The revision ID may change without notification |
3 | DRDY MODE | R/W | 0h | Data ready mode setting.
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the dedicated DRDY pin continues to indicate data ready, active low. 0: DOUT/DRDY pin functions only as data out (default) 1: DOUT/DRDY pin functions both as data out and data ready, active low(1) |
2-0 | IMAG[2:0] | R/W | 0h | IDAC excitation current magnitude.
The device has two excitation current sources (IDACs) that can be used for sensor excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the internal reference to be on. 000: off (default) 001: 50 µA 010: 100 µA 011: 250 µA 100: 500 µA 101: 750 µA 110: 1000 µA 111: 1500 µA |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I1DIR[3:0] | I2DIR[3:0] | ||||||
R/W-Fh | R/W-Fh |
LEGEND: R/W = Read/Write; -n = value after reset |
The two IDACs can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7-4 | I1DIR[3:0] | R/W | Fh | IDAC excitation current output 1.
These bits select the output pin for the first excitation current source. 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 10x0: IEXC1 10x1: IEXC2 11xx: Disconnected (default) |
3-0 | I2DIR[3:0] | R/W | Fh | IDAC excitation current output 2.
These bits select the output pin for the second excitation current source. 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 10x0: IEXC1 10x1: IEXC2 11xx: Disconnected (default) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOCFG[7:0] | |||||||
R/W-00h |
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | IOCFG[7] | R/W | 0h | GPIO[7] (AIN7) pin configuration.
0: GPIO[7] is not enabled (default) 1: GPIO[7] is applied to AIN7 |
6 | IOCFG[6] | R/W | 0h | GPIO[6] (AIN6) pin configuration.
0: GPIO[6] is not enabled (default) 1: GPIO[6] is applied to AIN6 |
5 | IOCFG[5] | R/W | 0h | GPIO[5] (AIN5) pin configuration.
0: GPIO[5] is not enabled (default) 1: GPIO[5] is applied to AIN5 |
4 | IOCFG[4] | R/W | 0h | GPIO[4] (AIN4) pin configuration.
0: GPIO[4] is not enabled (default) 1: GPIO[4] is applied to AIN4 |
3 | IOCFG[3] | R/W | 0h | GPIO[3] (AIN3) pin configuration.
0: GPIO[3] is not enabled (default) 1: GPIO[3] is applied to AIN3 |
2 | IOCFG[2] | R/W | 0h | GPIO[2] (AIN2) pin configuration.
0: GPIO[2] is not enabled (default) 1: GPIO[2] is applied to AIN2 |
1 | IOCFG[1] | R/W | 0h | GPIO[1] (REFN0) pin configuration.
0: GPIO[1] is not enabled (default) 1: GPIO[1] is applied to REFN0 |
0 | IOCFG[0] | R/W | 0h | GPIO[0] (REFP0) pin configuration.
0: GPIO[0] is not enabled (default) 1: GPIO[0] is applied to REFP0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IODIR[7:0] | |||||||
R/W-00h |
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | IODIR[7] | R/W | 0h | GPIO[7] (AIN7) pin direction.
This bit configures GPIO[7] as a GPIO input or GPIO output. 0: GPIO[7] is an output (default) 1: GPIO[7] is an input |
6 | IODIR[6] | R/W | 0h | GPIO[6] (AIN6) pin direction.
This bit configures GPIO[6] as a GPIO input or GPIO output. 0: GPIO[6] is an output (default) 1: GPIO[6] is an input |
5 | IODIR[5] | R/W | 0h | GPIO[5] (AIN5) pin direction.
This bit configures GPIO[5] as a GPIO input or GPIO output. 0: GPIO[5] is an output (default) 1: GPIO[5] is an input |
4 | IODIR[4] | R/W | 0h | GPIO[4] (AIN4) pin direction.
This bit configures GPIO[4] as a GPIO input or GPIO output. 0: GPIO[4] is an output (default) 1: GPIO[4] is an input |
3 | IODIR[3] | R/W | 0h | GPIO[3] (AIN3) pin direction.
This bit configures GPIO[3] as a GPIO input or GPIO output. 0: GPIO[3] is an output (default) 1: GPIO[3] is an input |
2 | IODIR[2] | R/W | 0h | GPIO[2] (AIN2) pin direction.
This bit configures GPIO[2] as a GPIO input or GPIO output. 0: GPIO[2] is an output (default) 1: GPIO[2] is an input |
1 | IODIR[1] | R/W | 0h | GPIO[1] (REFN0) pin direction.
This bit configures GPIO[1] as a GPIO input or GPIO output. 0: GPIO[1] is an output (default) 1: GPIO[1] is an input |
0 | IODIR[0] | R/W | 0h | GPIO[0] (REFP0) pin direction.
This bit configures GPIO[0] as a GPIO input or GPIO output. 0: GPIO[0] is an output (default) 1: GPIO[0] is an input |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IODAT[7:0] | |||||||
R/W-00h |
LEGEND: R/W = Read/Write; -n = value after reset |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
7 | IODAT[7] | R/W | 0h | GPIO[7] (AIN7) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[7] is low (default) 1: GPIO[7] is high |
6 | IODAT[6] | R/W | 0h | GPIO[6] (AIN6) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[6] is low (default) 1: GPIO[6] is high |
5 | IODAT[5] | R/W | 0h | GPIO[5] (AIN5) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[5] is low (default) 1: GPIO[5] is high |
4 | IODAT[4] | R/W | 0h | GPIO[4] (AIN4) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[4] is low (default) 1: GPIO[4] is high |
3 | IODAT[3] | R/W | 0h | GPIO[3] (AIN3) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[3] is low (default) 1: GPIO[3] is high |
2 | IODAT[2] | R/W | 0h | GPIO[2] (AIN2) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[2] is low (default) 1: GPIO[2] is high |
1 | IODAT[1] | R/W | 0h | GPIO[1] (REFN0) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[1] is low (default) 1: GPIO[1] is high |
0 | IODAT[0] | R/W | 0h | GPIO[0] (REFP0) pin data.
When configured as an output, a read to this bit returns the register value. When configured as an input, a write to this bit only sets the register value. 0: GPIO[0] is low (default) 1: GPIO[0] is high |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The ADS1148-Q1 offers many integrated features to ease the measurement of the most common sensor types, including various types of temperature and bridge sensors. Primary considerations when designing an application with this device include connecting and configuring the serial interface, designing the analog input filtering, establishing an appropriate external reference for ratiometric measurements, and setting the common-mode input voltage for the internal PGA. These considerations are discussed in this section.
Figure 64 shows the principle serial interface connections for the ADS1148-Q1.
Most microcontroller SPI peripherals can operate with the ADS1148-Q1. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the device can be found in the Timing Requirements section.
47-Ω resistors are recommended to be placed in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, DRDY, RESET, and START). This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines.
Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and second, to reduce external noise from being a part of the measurement.
As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the actual frequency band of interest below half the sampling frequency. Note that inside a ΔΣ ADC, the input signal is sampled at the modulator frequency, fMOD and not at the output data rate. The filter response of the digital filter repeats at multiples of the fMOD, as shown in Figure 65. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter, depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency or multiples thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter.
Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However, any noise pickup along the sensor wiring or the application circuitry can potentially alias into the pass band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result.
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1148-Q1 attenuates signals to a certain degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or 10 times higher is generally a good starting point for a system design.
Internal to the device, prior to the PGA inputs, is an EMI filter; see Figure 18. The cutoff frequency of this filter is approximately 47 MHz, which helps reject high-frequency interferences.
The full-scale range of the ADS1148-Q1 is defined by the reference voltage and the PGA gain (FSR = ±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to the specific system requirements. An external reference must be used if VIN is greater than 2.048 V. For example, an external 2.5-V reference is required to measure signals as large as 2.5 V. Note that the input signal must be within the common-mode input range to be valid, and that the reference input voltage must be between 0.5 V and (AVDD – AVSS – 1 V).
The buffered reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric measurement, the same excitation source that is used to excite the sensor is also used to establish the reference for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with the element being measured. The voltage that develops across the reference element is used as the reference source for the ADC. In this configuration, current noise and drift are common to both the sensor measurement and the reference; therefore, these components cancel out in the ADC transfer function. The output code is only a ratio of the sensor element value and the reference resistor value, and is not affected by the absolute value of the excitation current.
The ADS1148-Q1 is used to measure various types of signal configurations. However, configuring the input of the device properly for the respective signal type is important.
The ADS1148-Q1 features an 8-input multiplexer. Each input can be independently selected as the positive input or the negative input to be measured by the ADC. With an 8-input multiplexer, four independent differential-input channels can be measured. Seven channels can also be chosen to be measured, using one input as a fixed common input. Regardless of the analog input configuration, make sure that all inputs, including the common input are within the common-mode input voltage range.
If the supply is unipolar (for example, AVSS = 0 V and AVDD = 5 V), then V(AINN) = 0 V is not within the common-mode input range as given by Equation 3. Therefore, a single-ended measurement with the common input connected to ground is not possible. The common input is recommended to be connected to mid-supply, or alternatively to VREFOUT. Note that the common-mode range becomes further restricted with increasing PGA gain.
If the supply is bipolar (AVSS = –2.5 V and AVDD = 2.5 V), then ground is within the common-mode input range. Single-ended measurements with the common input connected to 0 V are possible in this case.
For a detailed explanation of the common-mode input range in relation to the PGA, see the PGA Common-Mode Voltage Requirements section.
Isolated sensors (sensors that are not referenced to the ADC ground) must have a common-mode voltage established within the specified ADC input range. Level shift the common-mode voltage by external resistor biasing, by connecting the negative lead to ground (bipolar analog supply), or by connecting to a dc voltage (unipolar analog supply). The 2.048-V reference output voltage can also be used to provide level shifting to floating sensor inputs.
To minimize leakage currents on the analog inputs, leave unused analog inputs floating, or connect these inputs to mid-supply or to AVDD. Connecting unused analog inputs to AVSS is possible as well, but can yield higher leakage currents than the options mentioned previously.
Do not float unused digital inputs or excessive power-supply leakage current may result. Tie all unused digital inputs to the appropriate levels, DVDD or DGND, even when in power-down mode. If the DRDY output is not used, leave the pin unconnected or tied to DVDD using a weak pullup resistor.
The following list shows a pseudo code sequence with the required steps to set up the device and the microcontroller that interfaces to the ADC to take subsequent readings from the ADS1148-Q1 in stop read data continuous (SDATAC) mode. In SDATAC mode, waiting for a time period longer than the data rate to retrieve the conversion result is sufficient. New conversion data does not interrupt the reading of registers or data on DOUT. However in this example, the dedicated DRDY pin is used to indicate the availability of new conversion data instead of waiting a set time period for a readout. The default configuration register settings are changed to PGA gain = 16, using the internal reference and a data rate of 20 SPS.
Power up;
Delay for a minimum of 16 ms to allow power supplies to settle and power-on reset to complete;
Enable the device by setting the START pin high;
Configure the serial interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA =1);
If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output;
Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt input;
Set CS to the device low;
Delay for a minimum of tCSSC;
Send the RESET command (06h) to make sure the device is properly reset after power up;
Delay for a minimum of 0.6 ms;
Send the SDATAC command (16h) to prevent the new data from interrupting data or register transactions;
Write the respective register configuration with the WREG command (40h, 03h, 01h, 00h, 03h and 42h);
As an optional sanity check, read back all configuration registers with the RREG command (four bytes from 20h, 03h);
Send the SYNC command (04h) to start the ADC conversion;
Delay for a minimum of tSCCS;
Clear CS to high (resets the serial interface);
Loop
{
Wait for DRDY to transition low;
Take CS low;
Delay for a minimum of tCSSC;
Send the RDATA command (12h);
Send 16 SCLKs to read out conversion data on DOUT/DRDY;
Delay for a minimum of tSCCS;
Clear CS to high;
}
Take CS low;
Delay for a minimum of tCSSC;
Send the SLEEP command (02h) to stop conversions and put the device in power-down mode;
This example explains a method to use the device with two sensors connected to two different analog channels. Figure 66 shows the sequence of SPI operations performed on the device. After power-up, 216 tCLK cycles are required before communication can be started. During the first 216 tCLK cycles, the device is internally held in a reset state. In this example, one of the sensors is connected to channels AIN0 and AIN1 and the other sensor is connected to channels AIN2 and AIN3. The ADC is operated at a data rate of 2 kSPS. The PGA gain is set to 32 for both sensors. VBIAS is connected to the negative terminal of both sensors (that is, channels AIN1 and AIN3). All these settings can be changed by performing a block write operation on the first four registers of the device. After the DRDY pin goes low, the conversion result can be immediately retrieved by sending in 16 SCLK pulses because the device defaults to RDATAC mode. When the conversion result is being retrieved, the active input channels can be switched to AIN2 and AIN3 by writing into the MUX0 register in a full-duplex manner, as shown in Figure 66. The write operation is completed with an additional eight SCLK pulses. The time from the write operation into the MUX0 register to the next DRDY low transition is shown in Figure 66 and is 0.513 ms in this case. After DRDY goes low, the conversion result can be retrieved and the active channel can be switched as before.
This second example deals with performing one conversion after power-up and then entering power-down mode. In this example, a sensor is connected to input channels AIN0 and AIN1. Commands to set up the device must occur at least 216 system clock cycles after powering up the device. The ADC operates at a data rate of 2 kSPS. The PGA gain is set to 32. VBIAS is connected to the negative terminal of the sensor (that is, channel AIN1). All these settings can be changed by performing a block write operation on the first four registers of the device. After performing the block write operation, the START pin can be taken low. The device enters the power-down mode as soon as DRDY goes low 0.575 ms after writing to the SYS0 register. The conversion result can be retrieved even after the device enters power-down mode by sending 16 SCLK pulses. Figure 67 shows the SPI communication sequence for entering power-down mode after a conversion.
Figure 68 shows a 3-wire RTD application circuit with lead-wire compensation using the ADS1148-Q1. The two IDAC current sources integrated in the ADS1148-Q1 are used to implement the lead-wire compensation. One IDAC current source (IDAC1) provides excitation to the RTD element. The other current source (IDAC2) has the same current setting, providing cancellation of lead-wire resistance by generating a voltage drop across the lead-wire resistance RLEAD2 equal to the voltage drop across RLEAD1. The voltages across the lead-wire resistances cancel because the voltage across the RTD is measured differentially at ADC pins AIN1 and AIN2. The ADC reference voltage (pins REFP0 and REFN0) is derived from the voltage across RREF with the currents from IDAC1 and IDAC2, providing ratiometric cancellation of the current-source drift. RREF also level shifts the RTD signal to within the ADC specified common-mode input range.
Table 29 shows the design requirements of the 3-wire RTD application.
PARAMETER | VALUE |
---|---|
Supply voltage | 3.3 V |
Data rate | 20 SPS |
RTD type | 3-wire PT100 |
RTD excitation current | 1 mA |
Temperature | –200°C to +850°C |
Calibrated temperature measurement accuracy at TA = 25°C(1) |
±0.2°C |
Figure 69 shows the basic topology of a ratiometric measurement using an RTD. Shown are the ADC with the RTD and a reference resistor RREF. A single current source, labeled IDAC1, is used to excite the RTD as well as to establish a reference voltage for the ADC across RREF.
With IDAC1, the ADC measures the RTD voltage using the voltage across RREF as the reference. This process gives a measurement such that the output code is proportional to the ratio of the RTD voltage and the reference voltage, as shown in Equation 21 and Equation 22.
The currents cancel so that Equation 22 reduces to Equation 23:
As shown in Equation 23, the measurement depends on the resistive value of the RTD and the reference resistor RREF, but not on the IDAC1 current value. Therefore, the absolute accuracy and temperature drift of the excitation current does not matter. This measurement is ratiometric. As long as there is no current leakage from IDAC1 outside of this circuit, the measurement depends only on RRTD and RREF.
In Figure 70, the lead resistances of a 3-wire RTD are shown and another excitation current source is added, labeled IDAC2.
With a single excitation current source, RLEAD1 adds an error to the measurement. By adding IDAC2, the second excitation current source is used to cancel out the error in the lead wire resistance. When adding the lead resistances and the second current source, Equation 22 becomes:
If the lead resistances match and the excitation currents match, then RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2. The lead wire resistances cancel out so that Equation 24 reduces to the result in Equation 25, thus maintaining a ratiometric measurement.
RLEAD3 is not part of the measurement because this lead resistance is not in the input measurement path or in the reference input path.
As Equation 24 shows, the two current sources must be matched to cancel the lead resistances of the RTD wires. Any mismatch in the two current sources is minimized by using the multiplexer to swap or chop the two current sources between the two inputs. Taking measurements in both configurations and averaging the readings reduces the effects of mismatched current sources. The design uses the multiplexer in the ADS1148-Q1 to implement this chopping technique to remove the mismatch error between IDAC1 and IDAC2.
The RTD is first chosen to be a PT100 element. The RTD resistance is defined by the Callendar-Van Dusen (CVD) equations and the resistance of the RTD is known depending on the temperature. The PT100 RTD has an impedance of 100 Ω at 0˚C and roughly 0.385 Ω of resistance change per 1˚C in temperature change. With a desired temperature measurement accuracy of 0.2˚C, this value translates to a resistive measurement accuracy of approximately 0.077 Ω. The RTD resistance at the low end of the temperature range of –200˚C is 18.59 Ω and the resistance at the high end of the temperature range of 850˚C is 390.48 Ω.
For the best possible resolution, the voltage across the RTD must be made as large as possible compared to the noise floor in the measurement. In general, measurement resolution improves with increasing excitation current. However, a larger excitation current creates self-heating in the RTD that causes drift and error in the measurement. The selection of excitation currents trades off resolution against sensor self-heating.
The excitation current sources in this design are selected to be 1 mA. This selection maximizes the value of the RTD voltage and keeps the self-heating low. The typical range of RTD self-heating coefficients is 2.5 mW/°C for small, thin-film elements and 65 mW/°C for larger, wire-wound elements. With a 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less than 0.4 mW and keeps the measurement errors resulting from self-heating to less than 0.01˚C.
As mentioned in the Topology section, chopping of the excitation current sources cancels mismatches between the IDACs. This technique is necessary for obtaining the best possible accuracy from the system. Mismatch between the excitation current sources is a large source of error if chopping is not implemented.
The internal reference voltage must be enabled when using the IDACs, even if an external ratiometric measurement is used for ADC conversions.
Table 30 shows the ADS1148-Q1 register settings for setting up the internal reference and the excitation current sources.
REGISTER | ADDRESS | BIT NAME | BIT VALUES | COMMENT |
---|---|---|---|---|
MUX1(1) | 02h | VREFCON[1:0] | 01 | Internal reference enabled |
MUX1 | 02h | REFSELT[1:0] | 00 | REFP0 and REFN0 reference inputs selected |
IDAC0 | 0Ah | IMAG[2:0] | 110 | IDAC magnitude = 1 mA |
IDAC1 | 0Bh | I1DIR[3:0](2) | 0000 | IDAC1 = AIN0 |
IDAC1 | 0Bh | I2DIR[3:0](2) | 0011 | IDAC2 = AIN3 |
The common-mode voltage of the measurement is recommended to be set near mid-supply, which helps keep the input within the common-mode input range of the PGA.
The reference resistor is selected to be 820 Ω. The voltage across RREF is calculated from Equation 26.
With AVDD = 3.3 V, Equation 26 shows that the input voltage is just below mid-supply.
The excitation current sources operate properly to a maximum IDAC compliance voltage. The current sources lose current regulation above this compliance voltage. In this example, the output voltage of the excitation current source is calculated from the sum of the voltages across the RTD and RREF, as shown in Equation 27.
A compliance voltage of 3.3 V – 2.04 V = 1.26 V is sufficient for proper IDAC operation. See Figure 9 and Figure 10 in the Typical Characteristics section for details.
Because the voltage across RREF sets the reference voltage for the ADC, the tolerance and temperature drift of RREF directly affects the measurement gain. A resistor with a 0.01% maximum tolerance is selected for this measurement.
Because the excitation current is small to reduce self-heating, the PGA in the ADS1148-Q1 is used to amplify the signal across the RTD to use the full-scale range of the ADC. Starting with the reference voltage, the ADC is able to measure a differential input signal range of ±1.64 V. The maximum allowable PGA gain setting is based on the reference voltage, the maximum RTD resistance, and the excitation current.
As mentioned previously, the resistance of the RTD is a maximum of 850°C. The voltage measured at this temperature is at maximum and is given by:
where
With a reference voltage of 1.64 V, the maximum gain for the PGA, without overranging the ADC, is shown in Equation 29.
Selecting a PGA gain of 4 gives a maximum measurement of 95% of the positive full-scale range. Table 31 shows the register settings to set the PGA gain as well as the inputs for the ADC.
REGISTER | ADDRESS | BIT NAME | BIT VALUES | COMMENT |
---|---|---|---|---|
MUX0 | 01h | MUX_SP[2:0] | 001 | AINP = AIN1 |
MUX0 | 01h | MUX_SN[2:0] | 010 | AINN = AIN2 |
SYS0 | 03h | PGA[2:0] | 010 | PGA Gain = 4 |
Now that the component values are selected, the common-mode input range must be verified to ensure that the ADC and PGA are not limited in operation. Start with the maximum input voltage, which gives the most restriction in the common-mode input range. At the maximum input voltage, the common-mode input voltage detected by the ADC is shown in Equation 30.
As mentioned in the Low-Noise PGA section, the common-mode input range is shown in Equation 3 and is applied to Equation 31.
After substituting in the appropriate values, the common-mode input range can be found in Equation 32 and Equation 33.
Because VCM = 1.835 V is within the limits of Equation 33, the RTD measurement is within the input common-mode range of the ADC and PGA. At the RTD voltage minimum (VRTD MIN = 18.59 mV), a similar calculation can be made to show that the input common-mode voltage is within the range as well.
The differential filters chosen for this application are designed to have a –3-dB corner frequency at least 10 times larger than the bandwidth of the ADC. The selected ADS1148-Q1 sampling rate of 20 SPS results in a –3-dB bandwidth of 14.8 Hz. The –3-dB filter corner frequency is set to be roughly 250 Hz at a mid-scale measurement resistance. For proper operation, the differential cutoff frequencies of the reference and input low-pass filters must be well matched. This matching can be difficult because when the resistance of the RTD changes over the span of the measurement, the filter cutoff frequency changes as well. To mitigate this effect, the two resistors used in the input filter (RI1 and RI2) are chosen to be two orders of magnitude larger than the RTD. Input bias currents of the ADC causes a voltage drop across the filter resistors that shows up as a differential offset error if the bias currents or filter resistors are not equal. The resistors are recommended to be limited to at most 10 kΩ to reduce dc offset errors resulting from the input bias current. RI1 and RI2 are chosen to be 4.7 kΩ.
The input filter differential capacitor (CI_DIFF) is calculated starting from the cutoff frequency, as shown in Equation 34 and Equation 35.
After solving for CI_DIFF, the capacitor is chosen to be a standard value of 68 nF.
To ensure that mismatch of the common-mode filter capacitors does not translate to a differential voltage, the common-mode capacitors (CI_CM1 and CI_CM2) are chosen to be 10 times smaller than the differential capacitor, making each capacitor 6.8 nF. These capacitor values result in a common-mode cutoff frequency that is roughly 20 times larger than the differential filter, making the matching of the common-mode cutoff frequencies less critical.
After substituting values into Equation 36 and Equation 37, the common-mode cutoff frequencies are found to be f–3dB_CM+ = 4.13 kHz and f–3dB_CM– = 4.24 kHz, respectively.
Often, filtering the reference input is not necessary and adding bulk capacitance at the reference input is sufficient. However, equations showing a design procedure calculating filter values for the reference inputs are shown in Equation 38 and Equation 39.
The differential reference filter is designed to have a –3-dB corner frequency of 250 Hz to match the differential input filter. The two reference filter resistors are selected to be 9.09 kΩ, which is several times larger than the value of RREF. The reference filter resistors must not be sized larger than 10 kΩ or dc bias errors become significant. The differential capacitor for the reference filter is calculated as shown in Equation 38.
After solving for CR_DIFF, the capacitor is chosen to be a standard value of 33 nF.
To ensure that mismatch of the common-mode filter capacitors does not translate to a differential voltage, the reference common-mode capacitors (CR_CM1 and CR_CM2) are chosen to be 10 times smaller than the reference differential capacitor, making these capacitors each 3.3 nF. Again, the resulting cutoff frequency for the common-mode filters is roughly 20 times larger than the differential filter, making the matching of the cutoff frequencies less critical.
After substituting values into Equation 40 and Equation 41, common-mode cutoff frequencies for the reference filter are found to be f–3dB_CM+ = 4.87 kHz and f–3dB_CM+ = 5.31 kHz, respectively.
The register settings for this design are shown in Table 32.
REGISTER ADDRESS | REGISTER NAME | SETTING | DESCRIPTION |
---|---|---|---|
00h | MUX0 | 0Ah | Select AINP = AIN1 and AINN = AIN2 |
01h | VBIAS | 00h | — |
02h | MUX1 | 20h | Internal reference enabled, REFP0 and REFN0 reference inputs selected |
03h | SYS0 | 22h | PGA gain = 4, DR = 20 SPS |
04h | OFC0(1) | xxh | — |
05h | OFC1 | xxh | — |
06h | OFC2 | xxh | — |
07h | FSC0(1) | xxh | — |
08h | FSC1 | xxh | — |
09h | FSC2 | xxh | — |
0Ah | IDAC0 | x6h | ID bits can be version dependent, IDAC magnitude set to 1 mA |
0Bh | IDAC1 | 03h(2) | IDAC1 set to AIN0; IDAC2 set to AIN3 |
0Ch | GPIOCFG | 00h | — |
0Dh | GPIOCDIR | 00h | — |
0Eh | GPIODAT | 00h | — |
To test the accuracy of the acquisition circuit, a series of calibrated, high-precision discrete resistors are used as the input to the system. Measurements are taken at TA = 25°C. Figure 71 displays the uncalibrated resistance measurement accuracy of the system over an input span from 20 Ω to 400 Ω. For each resistor value, 512 measurements are taken. With each measurement, IDAC1 and IDAC2 are chopped to remove the excitation current mismatch.
The uncalibrated measurement error is displayed in Figure 72. The offset and gain error can be primarily attributed to the offset and gain error of the ADC. However, the accuracy of RREF contributes directly to the accuracy of the measurement. To keep the gain error low, RREF must be a low-drift precision resistor.
Precision temperature measurement applications are typically calibrated to remove the effects of gain and offset errors, which generally dominate the total system error. The simplest calibration method is a linear, or two-point, calibration that applies an equal and opposite gain and offset term to cancel the measured system gain and offset errors. Using the results of Figure 72, the uncalibrated gain and offset error are then used to modify the offset calibration and the full-scale calibration registers in the device. The results of this calibrated system measurement are shown in Figure 73.
The results in Figure 73 are converted to temperature accuracy by dividing the results by the RTD sensitivity (α) at the measured resistance. Over the full resistance input range, the maximum total measured error is ±0.011 Ω. Equation 42 uses the measured resistance error and the nominal RTD sensitivity to calculate the measured temperature accuracy.
Figure 74 displays the calculated temperature measurement accuracy of the circuit assuming a linear RTD resistance to temperature response. Figure 74 does not include any linearity compensation of the RTD.
Table 33 compares the measurement accuracy with the design goal from Table 29.
PARAMETER | GOAL | MEASURED | |
---|---|---|---|
Calibrated resistance measurement accuracy at TA = 25ºC | ±0.077 Ω | ±0.011 Ω | |
Calibrated temperature measurement accuracy at TA = 25ºC | ±0.2°C | ±0.029°C |
Figure 75 shows the basic connections of a thermocouple measurement system. This circuit uses a cold-junction compensation measurement based on the Ratiometric 3-Wire RTD Measurement System topology described in the Ratiometric 3-Wire RTD Measurement System example. Using the IEXC1 and IEXC2 pins allows for routing of the IDAC currents without using any other analog pins. Along with the thermocouple and cold-junction measurements, four other analog inputs (AIN4 to AIN7, not shown in the schematic) are available for alternate measurements or use as GPIO pins.
Table 34 shows the design requirements of the thermocouple application.
PARAMETER | VALUE |
---|---|
Supply voltage | 3.3 V |
Reference voltage | Internal 2.048-V reference |
Update rate | ≥ 10 readings per second |
Thermocouple type | K |
Temperature measurement | –200ºC to +1250ºC |
Measurement accuracy at TA = 25ºC(1) | ±0.5ºC |
The biasing resistors RB1 and RB2 are used to set the common-mode voltage of the thermocouple to within the specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). If the application requires the thermocouple to be biased to GND, a bipolar supply (for example, AVDD = 2.5 V and AVSS = –2.5 V) must be used for the device to meet the common-mode voltage requirement of the PGA. When choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ to 50 MΩ.
In addition to biasing the thermocouple, RB1 and RB2 are also useful for detecting an open thermocouple lead. When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition.
Although the digital filter attenuates high-frequency components of noise, a first-order, passive RC filter is recommended to be provided at the inputs to further improve performance. The differential RC filter formed by RI1, RI2, and the differential capacitor CI_DIFF offers a cutoff frequency that is calculated using Equation 43.
Two common-mode filter capacitors (CI_CM1 and CI_CM2) are also added to offer attenuation of high-frequency, common-mode noise components. The differential capacitor CI_DIFF is recommended to be at least an order of magnitude (10 times) larger than the common-mode capacitors (CI_CM1 and CI_CM2) because mismatches in the common-mode capacitors can convert common-mode noise into differential noise.
The filter resistors RF1 and RF2 also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occurs. Care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. For thermocouple measurements, limit the filter resistor values to below 10 kΩ.
The filter component values used in this design are: RI1 = RI2 = 1 kΩ, CI_DIFF = 100 nF, and CI_CM1 = CI_CM2 = 10 nF.
The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple voltage occurs at TTC = 1250°C and is VTC = 50.644 mV, as defined in the tables published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature of TCJ = 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at TTC = 1250°C produces an output voltage of VTC = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction temperature of TCJ = –40°C. The maximum gain that can be applied when using the internal 2.048-V reference is then calculated as 39.3 from Equation 44. The next smaller PGA gain setting the device offers is 32.
AIN2 and AIN3 are attached to a 3-wire RTD that is used to measure the cold-junction temperature. Similar to the example in the Ratiometric 3-Wire RTD Measurement System section, the 3-wire RTD design is the same except the inputs and excitation current sources have been changed. Note that RREF and PGA Gain can be optimized for a reduced temperature range.
The device does not perform an automatic cold-junction compensation of the thermocouple. This compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one or multiple readings of the thermocouple voltage from the device and then sets the device to measure the cold junction with the RTD to compensate for the cold-junction temperature.
An algorithm similar to the following must be implemented on the microcontroller to compensate for the cold-junction temperature:
There are alternate methods of measuring the cold-junction temperature. The additional analog input channels of the device can be used in this case to measure the cold-junction temperature with a thermistor or an alternate analog temperature sensor.
To get an approximation of the achievable temperature resolution, the peak-to-peak noise of the ADS1148-Q1 at gain = 32 and DR = 20 SPS (1.95 µVPP) is taken from Table 1. The noise is divided by the average sensitivity of a K-type thermocouple (41 µV/°C), as shown in Equation 45.
The register settings for this design are shown in Table 35. The inputs are selected to measure the thermocouple and the internal reference is enabled and selected. The excitation current sources are also enabled and selected. Although this configuration consumes some power, this setting allows for a quick transition for the cold-junction measurement.
REGISTER ADDRESS | REGISTER NAME | SETTING | DESCRIPTION |
---|---|---|---|
00h | MUX0 | 01h | Select AINP = AIN0, AINN = AIN1 |
01h | VBIAS | 00h | — |
02h | MUX1 | 30h | Internal reference enabled, internal reference selected |
03h | SYS0 | 52h | PGA gain = 32, DR = 20 SPS |
04h | OFC0 | xxh | — |
05h | OFC1 | xxh | — |
06h | OFC2 | xxh | — |
07h | FSC0 | xxh | — |
08h | FSC1 | xxh | — |
09h | FSC2 | xxh | — |
0Ah | IDAC0 | x6h | IDAC magnitude set to 1 mA |
0Bh | IDAC1 | 89h | IDAC1 set to IEXC1, IDAC2 set to IEXC2 |
0Ch | GPIOCFG | 00h | — |
0Dh | GPIOCDIR | 00h | — |
0Eh | GPIODAT | 00h | — |
Changing to the cold-junction measurement, the registers are set to measure the RTD. This measurement requires changing the input, the reference input, the gain, and any calibration settings required for the measurement accuracy. Table 36 shows the register settings for the RTD measurement used for cold-junction compensation.
REGISTER ADDRESS | REGISTER NAME | SETTING | DESCRIPTION |
---|---|---|---|
00h | MUX0 | 13h | Select AINP = AIN2, AINN = AIN3 |
01h | VBIAS | 00h | — |
02h | MUX1 | 20h | Internal reference enabled, REFP0 and REFN0 selected |
03h | SYS0 | 22h | PGA gain = 4, DR = 20 SPS |
04h | OFC0 | xxh | Calibration values are different between measurement settings |
05h | OFC1 | xxh | — |
06h | OFC2 | xxh | — |
07h | FSC0 | xxh | — |
08h | FSC1 | xxh | — |
09h | FSC2 | xxh | — |
0Ah | IDAC0 | x6h | IDAC magnitude set to 1 mA |
0Bh | IDAC1 | 89h | IDAC1 set to IEXC1, IDAC2 set to IEXC2 |
0Ch | GPIOCFG | 00h | — |
0Dh | GPIOCDIR | 00h | — |
0Eh | GPIODAT | 00h | — |
Figure 76 illustrates the Do's and Don'ts of the ADC circuit connections.
The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V, AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels (with the exception of the GPIO levels that are set by the analog supply of AVDD to AVSS).
The power supplies can be sequenced in any order but in no case must any analog or digital inputs exceed the respective analog or digital power-supply voltage limits. Wait at least 216 tCLK cycles after all power supplies are stabilized before communicating with the device to allow the power-on reset process to complete.
Good power-supply decoupling is important to achieve optimum performance. AVDD, AVSS (when using a bipolar supply), and DVDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 77. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance connections. Use multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins can offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Connect analog and digital ground together as close to the device as possible.
Use best design practices when laying out a printed-circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout separates analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog multiplexers (MUXs)] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 78. Although Figure 78 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog component.
The following list outlines some basic recommendations for the layout of the ADS1148-Q1 to get the best possible performance of the ADC. A good design can be ruined with a bad circuit layout.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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