SBAS852A August 2017 – February 2020 ADS114S06B , ADS114S08B
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The ADS114S06B and ADS114S08B are precision, 16-bit, delta-sigma (ΔΣ), analog-to-digital converters (ADCs) that offer low power consumption and many integrated features to reduce system cost and component count in applications measuring small-signal sensors.
These ADCs feature a digital filter that offers low-latency conversion results and 50-Hz or 60-Hz rejection for noisy industrial environments. A low-noise, programmable gain amplifier (PGA) provides gains ranging from 1 to 128 to amplify low-level signals for resistive bridge or thermocouple applications. Additionally, these devices integrate a low-drift, 2.5-V reference that reduces printed circuit board (PCB) area. Finally, two programmable excitation current sources (IDACs) allow for easy and accurate RTD biasing.
An input multiplexer supports 12 inputs for the ADS114S08B and six inputs for the ADS114S06B that can be connected to the ADC in any combination for design flexibility. In addition, these devices include features such as sensor burn-out detection, voltage bias for thermocouples, system monitoring, and four general-purpose I/Os (GPIOs).
The devices are offered in a leadless VQFN-32 or a TQFP-32 package.
ORDER NUMBER | PACKAGE (PIN) | BODY SIZE |
---|---|---|
ADS114S0xB | TQFP (32) | 5.0 mm × 5.0 mm |
VQFN (32) | 5.0 mm × 5.0 mm |
Changes from * Revision (August 2017) to A Revision
PRODUCT | RESOLUTION (Bits) | NUMBER OF INPUTS |
---|---|---|
ADS114S08B | 16 | 12 analog inputs |
ADS114S06B | 16 | 6 analog inputs |
NOTE:
The analog input functions (AIN6–AIN11) are not available on pins 19 to 22, 31, and 32 for the ADS114S06B.PIN | FUNCTION | DESCRIPTION(1) | |
---|---|---|---|
NO. | NAME | ||
1 | AINCOM | Analog input | Common analog input for single-ended measurements |
2 | AIN5 | Analog input | Analog input 5 |
3 | AIN4 | Analog input | Analog input 4 |
4 | AIN3 | Analog input | Analog input 3 |
5 | AIN2 | Analog input | Analog input 2 |
6 | AIN1 | Analog input | Analog input 1 |
7 | AIN0 | Analog input | Analog input 0 |
8 | START/SYNC | Digital input | Start conversion |
9 | CS | Digital input | Chip select; active low |
10 | DIN | Digital input | Serial data input |
11 | SCLK | Digital input | Serial clock input |
12 | DOUT/DRDY | Digital output | Serial data output combined with data ready; active low |
13 | DRDY | Digital output | Data ready; active low |
14 | DGND | Digital ground | Digital ground |
15 | IOVDD | Digital supply | Digital I/O power supply. In case IOVDD is not tied to DVDD, connect a 100-nF (or larger) capacitor to DGND. |
16 | DVDD | Digital supply | Digital core power supply. Connect a 100-nF (or larger) capacitor to DGND. |
17 | CLK | Digital input | External clock input. Connect to DGND to use the internal oscillator. |
18 | RESET | Digital input | Reset; active low |
19 | GPIO3/AIN11 | Analog input/output | General-purpose I/O(2); analog input 11 (ADS114S08B only) |
20 | GPIO2/AIN10 | Analog input/output | General-purpose I/O(2); analog input 10 (ADS114S08B only) |
21 | GPIO1/AIN9 | Analog input/output | General-purpose I/O(2); analog input 9 (ADS114S08B only) |
22 | GPIO0/AIN8 | Analog input/output | General-purpose I/O(2); analog input 8 (ADS114S08B only) |
23 | REFOUT | Analog output | Positive voltage reference output. Connect a 1-µF to 47-µF capacitor to REFCOM if the internal voltage reference is enabled. |
24 | REFCOM | Analog output | Negative voltage reference output. Connect to AVSS. |
25 | NC | — | Leave unconnected or connect to AVSS |
26 | AVDD | Analog supply | Positive analog power supply. Connect a 330-nF (or larger) capacitor to AVSS. |
27 | AVSS | Analog supply | Negative analog power supply |
28 | AVSS | Analog supply | Negative analog power supply |
29 | REFN0 | Analog input | Negative external reference input 0 |
30 | REFP0 | Analog input | Positive external reference input 0 |
31 | REFN1/AIN7 | Analog input | Negative external reference input 1; analog input 7 (ADS114S08B only) |
32 | REFP1/AIN6 | Analog input | Positive external reference input 1; analog input 6 (ADS114S08B only) |
Pad | Thermal Pad | — | RHB package only. Thermal power pad. Connect to AVSS. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | AVDD to AVSS | –0.3 | 5.5 | V |
AVSS to DGND | –2.8 | 0.3 | ||
DVDD to DGND | –0.3 | 3.9 | ||
IOVDD to DGND | –0.3 | 5.5 | ||
Analog input voltage | AINx, GPIOx, REFPx, REFNx, REFCOM | AVSS – 0.3 | AVDD + 0.3 | V |
Digital input voltage | CS, SCLK, DIN, DOUT/DRDY, DRDY,
START, RESET, CLK |
DGND – 0.3 | IOVDD + 0.3 | V |
Input current | Continuous, REFN0, REFOUT | –100 | 100 | mA |
Continuous, all other pins except power-supply pins | –10 | 10 | ||
Temperature | Junction, TJ | 150 | °C | |
Storage, Tstg | –60 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
Analog power supply | AVDD to AVSS | 2.7 | 5.25 | V | ||
AVSS to DGND | –2.625 | 0 | 0.05 | |||
AVDD to DGND | 1.5 | 5.25 | ||||
Digital core power supply | DVDD to DGND | 2.7 | 3.6 | V | ||
Digital IO power supply | IOVDD to DGND | DVDD | 5.25 | V | ||
ANALOG INPUTS(1) | ||||||
V(AINx) | Absolute input voltage(2) | PGA bypassed | AVSS – 0.05 | AVDD + 0.05 | V | |
PGA enabled, gain = 1 to 16 | AVSS + 0.15 + |VINMAX|·(Gain – 1) / 2 | AVDD – 0.15 – |VINMAX|·(Gain –1) / 2 | ||||
PGA enabled, gain = 32 to 128 | AVSS + 0.15 + 15.5·|VINMAX| | AVDD – 0.15 – 15.5·|VINMAX| | ||||
VIN | Differential input voltage | VIN = VAINP – VAINN | –VREF / Gain | VREF / Gain | V | |
VOLTAGE REFERENCE INPUTS(3) | ||||||
VREF | Differential reference input voltage | VREF = V(REFPx) – V(REFNx) | 0.5 | AVDD – AVSS | V | |
V(REFNx) | Absolute negative reference voltage | Negative reference buffer disabled | AVSS – 0.05 | V(REFPx) – 0.5 | V | |
Negative reference buffer enabled | AVSS | V(REFPx) – 0.5 | V | |||
V(REFPx) | Absolute positive reference voltage | Positive reference buffer disabled | V(REFNx) + 0.5 | AVDD + 0.05 | V | |
Positive reference buffer enabled | V(REFNx) + 0.5 | AVDD | V | |||
EXTERNAL CLOCK SOURCE(4) | ||||||
fCLK | External clock frequency | 2 | 4.096 | 4.5 | MHz | |
Duty cycle | 40% | 50% | 60% | |||
GENERAL-PURPOSE INPUTS (GPIOs) | ||||||
Input voltage | AVSS – 0.05 | AVDD + 0.05 | V | |||
DIGITAL INPUTS (Other than GPIOs) | ||||||
Input voltage | DGND | IOVDD | V | |||
TEMPERATURE RANGE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC | ADS114S06B, ADS114S08B | UNIT | ||
---|---|---|---|---|
VQFN (RHB) | TQFP (PBS) | |||
32 PINS | 32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 45.2 | 75.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 28.3 | 17.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.8 | 28.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.7 | 28.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||||
Absolute input current | PGA bypassed,
AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V |
±0.5 | nA | |||||
PGA enabled, gain 1 to 128,
V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX |
–10 | ±0.1 | 10 | |||||
Differential input current | PGA bypassed,
VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF |
±1 | nA/V | |||||
PGA enabled, gain 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain |
±0.02 | nA | ||||||
PGA | ||||||||
Gain settings | 1, 2, 4, 8, 16,
32, 64, 128 |
|||||||
Startup time | Enabling the PGA in conversion mode | 190 | µs | |||||
SYSTEM PERFORMANCE | ||||||||
Resolution (no missing codes) | 16 | Bits | ||||||
DR | Data rate | 2.5, 5, 10, 16.6,
20, 50, 60, 100, 200, 400, 800, 1000, 2000, 4000 |
SPS | |||||
INL | Integral nonlinearity (best fit) | PGA bypassed, VCM = AVDD / 2 | 1 | ppmFSR | ||||
PGA enabled, gain = 1 to 128, VCM = AVDD / 2 | 2 | 25 | ||||||
VIO | Input offset voltage | PGA bypassed | 20 | µV | ||||
PGA enabled, gain = 1 to 8 | 20 / Gain | |||||||
PGA enabled, gain = 16 to 128 | 2 | |||||||
PGA bypassed, after internal offset calibration | On the order of noisePP at the set DR and gain | |||||||
PGA enabled, gain = 1 to 128, after internal offset calibration | On the order of noisePP at the set DR and gain | |||||||
Offset drift | PGA bypassed | 10 | nV/°C | |||||
PGA enabled, gain = 1 to 128 | 15 | |||||||
Gain error(1) | TA = 25°C, PGA bypassed | 0.01% | 0.1% | |||||
TA = 25°C, PGA enabled, gain = 1 to 128 | 0.025% | 0.2% | ||||||
Gain drift(1) | PGA bypassed | 0.5 | ppm/°C | |||||
PGA enabled, gain = 1 to 128 | 1 | |||||||
Noise (input-referred) | See the Noise Performance section | |||||||
NMRR | Normal-mode rejection ratio(2) | fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS | 75 | 95 | dB | |||
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,
external fCLK = 4.096 MHz |
95 | |||||||
CMRR | Common-mode rejection ratio | At dc | 120 | dB | ||||
fCM = 50 Hz or 60 Hz (±1 Hz),
DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS |
125 | |||||||
PSRR | Power-supply rejection ratio | AVDD at dc | 105 | dB | ||||
AVDD at 50 Hz or 60 Hz | 115 | |||||||
DVDD at dc | 115 | |||||||
VOLTAGE REFERENCE INPUTS | ||||||||
Absolute input current | Reference buffers disabled, external VREF = 2.5 V,
REFP1/REFN1 inputs |
4 | µA/V | |||||
Reference buffers enabled, external VREF = 2.5 V,
REFP1/REFN1 inputs |
5 | nA | ||||||
INTERNAL VOLTAGE REFERENCE | ||||||||
VREF | Output voltage | 2.5 | V | |||||
Accuracy | TA = 25°C | –0.2% | ±0.01% | 0.2% | ||||
Temperature drift | 8 | 40 | ppm/°C | |||||
Output current | AVDD = 2.7 V to 3.3 V, sink and source | –5 | 5 | mA | ||||
AVDD = 3.3 V to 5.25 V, sink and source | –10 | 10 | ||||||
Short-circuit current limit | Sink and source | 70 | 100 | mA | ||||
PSRR | Power-supply rejection ratio | AVDD at dc | 85 | dB | ||||
Load regulation | AVDD = 2.7 V to 3.3 V,
load current = –5 mA to 5 mA |
8 | µV/mA | |||||
AVDD = 3.3 V to 5.25 V,
load current = –10 mA to 10 mA |
8 | |||||||
Startup time | 1-µF capacitor on REFOUT, 0.001% settling | 5.9 | ms | |||||
Capacitive load stability | Capacitor on REFOUT | 1 | 47 | µF | ||||
Reference noise | f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT | 9 | µVPP | |||||
INTERNAL OSCILLATOR | ||||||||
fCLK | Frequency | 4.096 | MHz | |||||
Accuracy | –2% | 2% | ||||||
EXCITATION CURRENT SOURCES (IDACS) | ||||||||
Current settings | 10, 50, 100,
250, 500, 750, 1000, 1500, 2000 |
µA | ||||||
Compliance voltage(3) | 10 µA to 750 µA, 0.1% deviation | AVSS | AVDD – 0.4 | V | ||||
1 mA to 2 mA, 0.1% deviation | AVSS | AVDD – 0.6 | ||||||
Accuracy (each IDAC) | TA = 25°C, 10 µA to 2 mA | –6% | ±1% | 6% | ||||
Current mismatch between IDACs | TA = 25°C, 10 µA to 2 mA | 0.2% | ||||||
Temperature drift (each IDAC) | 10 µA to 2 mA | 100 | ppm/°C | |||||
Temperature drift matching between IDACs | 10 µA to 2 mA | 10 | ppm/°C | |||||
Startup time | With internal reference already settled. From end of WREG command to current flowing out of pin. | 22 | µs | |||||
BIAS VOLTAGE | ||||||||
VBIAS | Output voltage | (AVDD + AVSS) / 2 | V | |||||
Output impedance | 350 | Ω | ||||||
Startup time | Combined capacitive load on all selected analog inputs CLOAD = 1 µF, 0.1% settling | 2.8 | ms | |||||
BURNOUT CURRENT SOURCES (BOCS) | ||||||||
Current settings | 0.2, 1, 10 | µA | ||||||
Accuracy | 0.2 µA, sinking or sourcing | ±8% | ||||||
1 µA, sinking or sourcing | ±4% | |||||||
10 µA, sinking or sourcing | ±2% | |||||||
EXTERNAL REFERENCE MONITOR | ||||||||
Threshold | 0.3 | V | ||||||
SUPPLY VOLTAGE MONITORS | ||||||||
Accuracy | (AVDD – AVSS) / 4 monitor | ±1% | ||||||
DVDD / 4 monitor | ±1% | |||||||
TEMPERATURE SENSOR | ||||||||
Output voltage | TA = 25°C | 129 | mV | |||||
Temperature coefficient | 403 | µV/°C | ||||||
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs) | ||||||||
VIL | Logic input level, low | AVSS – 0.05 | 0.3 AVDD | V | ||||
VIH | Logic input level, high | 0.7 AVDD | AVDD + 0.05 | V | ||||
VOL | Logic output level, low | IOL = 1 mA | AVSS | 0.2 AVDD | V | |||
VOH | Logic output level, high | IOH = 1 mA | 0.8 AVDD | AVDD | V | |||
DIGITAL INPUT/OUTPUTS | ||||||||
VIL | Logic input level, low | DGND | 0.3 IOVDD | V | ||||
VIH | Logic input level, high | 0.7 IOVDD | IOVDD | V | ||||
VOL | Logic output level, low | IOL = 1 mA | DGND | 0.2 IOVDD | V | |||
VOH | Logic output level, high | IOH = 1 mA | 0.8 IOVDD | IOVDD | V | |||
Input current | DGND ≤ VDigital Input ≤ IOVDD | –1 | 1 | µA | ||||
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Internal Oscillator, All Data Rates, VIN = 0 V) | ||||||||
IAVDD | Analog supply current | Power-down mode | 0.1 | µA | ||||
Standby mode, PGA bypassed | 70 | |||||||
Conversion mode, PGA bypassed | 85 | |||||||
Conversion mode, PGA enabled, gain = 1, 2 | 120 | |||||||
Conversion mode, PGA enabled, gain = 4, 8 | 140 | |||||||
Conversion mode, PGA enabled, gain = 16, 32 | 165 | |||||||
Conversion mode, PGA enabled, gain = 64 | 200 | |||||||
Conversion mode, PGA enabled, gain = 128 | 250 | |||||||
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V) | ||||||||
IAVDD | Analog supply current | Internal 2.5-V reference, no external load | 185 | µA | ||||
Positive reference buffer | 35 | |||||||
Negative reference buffer | 25 | |||||||
VBIAS buffer, no external load | 10 | |||||||
IDAC overhead, 10 µA to 250 µA | 20 | |||||||
IDAC overhead, 500 µA to 750 µA | 30 | |||||||
IDAC overhead, 1 mA | 40 | |||||||
IDAC overhead, 1.5 mA | 50 | |||||||
IDAC overhead, 2 mA | 65 | |||||||
Reference monitor circuit | 10 | |||||||
DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active) | ||||||||
IDVDD + IIOVDD | Digital supply current | Power-down mode, internal oscillator | 0.1 | µA | ||||
Standby mode, internal oscillator | 185 | |||||||
Conversion mode, internal oscillator | 225 | |||||||
Conversion mode, external fCLK = 4.096 MHz | 195 | |||||||
POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Internal Oscillator, All Data Rates, VIN = 0 V, SPI Not Active) | ||||||||
PD | Power dissipation | Conversion mode, PGA enabled, gain = 1 | 1.75 | mW |
MIN | MAX | UNIT(1) | ||
---|---|---|---|---|
SERIAL INTERFACE | ||||
td(CSSC) | Delay time, first SCLK rising edge after CS falling edge | 20 | ns | |
td(SCCS) | Delay time, CS rising edge after final SCLK falling edge | 20 | ns | |
tw(CSH) | Pulse duration, CS high | 30 | ns | |
tc(SC) | SCLK period | 100 | ns | |
tw(SCH) | Pulse duration, SCLK high | 40 | ns | |
tw(SCL) | Pulse duration, SCLK low | 40 | ns | |
tsu(DI) | Setup time, DIN valid before SCLK falling edge | 15 | ns | |
th(DI) | Hold time, DIN valid after SCLK falling edge | 20 | ns | |
td(CMD) | Delay time, between bytes or commands | 0 | ns | |
RESET PIN | ||||
tw(RSL) | Pulse duration, RESET low | 4 | tCLK | |
td(RSSC) | Delay time, first SCLK rising edge after RESET rising edge (or 7th SCLK falling edge of RESET command) | 4096 | tCLK | |
START/SYNC PIN | ||||
tw(STH) | Pulse duration, START/SYNC high | 4 | tCLK | |
tw(STL) | Pulse duration, START/SYNC low | 4 | tCLK | |
tsu(STDR) | Setup time, START/SYNC falling edge (or 7th SCLK falling edge of STOP command) before DRDY falling edge to stop further conversions (continuous conversion mode) | 32 | tCLK |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT(1) | |
---|---|---|---|---|---|---|
tp(CSDO) | Propagation delay time, CS falling edge to DOUT driven | 0 | 25 | ns | ||
tp(SCDO) | Propagation delay time, SCLK rising edge to valid new DOUT | 3 | 30 | ns | ||
tp(CSDOZ) | Propagation delay time, CS rising edge to DOUT high impedance | 0 | 25 | ns | ||
tp(STDR) | Propagation delay time, START/SYNC rising edge (or first SCLK rising edge of any command or data read) to DRDY rising edge | 2 | tCLK | |||
tw(DRH) | Pulse duration, DRDY high | 24 | tCLK | |||
tp(GPIO) | Propagation delay time, last SCLK falling edge of WREG command to GPIOx output valid | 3 | 100 | ns | ||
SPI timeout per 8 bits(2) | 215 | tCLK |
NOTE:
Single-byte communication is shown. Actual communication can be multiple bytes.NOTE:
Single-byte communication is shown. Actual communication can be multiple bytes.PGA bypassed, DR = 20 SPS, VIN = 0 V |
PGA enabled, gain = 1, DR = 20 SPS, VIN = 0 V |
PGA bypassed, DR = 20 SPS, VCM = 1.65 V |
PGA enabled, DR = 20 SPS, VCM = 1.65 V |
PGA bypassed, gain = 1 |
IDAC output voltage = 1.65 V |
AVDD = 3.3 V |
DVDD = 3.3 V |
Standby and conversion mode, external VREF |
Power-down mode |
Standby and conversion mode |
Power-down mode |
PGA bypassed, DR = 4 kSPS, VIN = 0 V |
PGA enabled, gain = 1, DR = 4 kSPS, VIN = 0 V |
PGA bypassed, DR = 4 kSPS, VCM = 1.65 V |
PGA enabled, DR = 4 kSPS, VCM = 1.65 V |
PGA enabled, gain = 1 |
28 units, TQFP package |
28 units | ||
AVDD = 3.3 V |
DVDD = 3.3 V |
Conversion mode, external VREF |
Conversion mode |
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called the oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.
Table 1 and Table 2 summarize the device noise performance. Data are representative of typical noise performance at TA = 25°C using the internal 2.5-V reference. Data shown are based on 512 consecutive samples from a single device with inputs internally shorted. Table 1 lists the input-referred root mean square noise in units of μVRMS for the conditions shown. Peak-to-peak (µVPP) values are shown in parentheses. Table 2 lists the corresponding data in effective resolution calculated from μVRMS values using Equation 1. Noise-free resolution is calculated from µVPP values using Equation 2.
The input-referred noise (Table 1) only changes marginally when using an external low-noise reference, such as the REF5025. To calculate effective resolution and noise-free resolution when using a reference voltage other than 2.5 V, use Equation 1 and Equation 2:
Noise performance with the PGA bypassed are identical to the noise performance of the device with gain = 1.
DATA RATE
(SPS) |
GAIN | |||||||
---|---|---|---|---|---|---|---|---|
1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | |
2.5 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.60) |
5 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.60) |
10 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.60) |
16.6 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.60) |
20 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.60) |
50 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.60) |
60 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.2) | 0.60 (0.90) |
100 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.4) | 0.60 (1.3) |
200 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.4) | 1.2 (1.9) | 0.60 (1.7) |
400 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (2.8) | 1.2 (2.9) | 0.60 (2.3) |
800 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (4.0) | 1.2 (3.8) | 0.60 (3.2) |
1000 | 76.3 (76.3) | 38.1 (38.1) | 19.1 (19.1) | 9.5 (9.5) | 4.8 (4.8) | 2.4 (5.1) | 1.2 (4.3) | 0.60 (3.8) |
2000 | 76.3 (83) | 38.1 (80) | 19.1 (32) | 9.5 (17) | 4.8 (11) | 2.4 (6.7) | 1.2 (6.6) | 1.0 (6.5) |
4000 | 103 (629) | 38.1 (404) | 24 (160) | 12 (70) | 6.4 (39) | 3.3 (21) | 3.1 (21) | 2.6 (20) |
DATA RATE
(SPS) |
GAIN | |||||||
---|---|---|---|---|---|---|---|---|
1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | |
2.5 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) |
5 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) |
10 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) |
16.6 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) |
20 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) |
50 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.5) |
60 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.4) |
100 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.8) | 16 (14.9) |
200 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.3) | 16 (14.5) |
400 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.8) | 16 (14.7) | 16 (14.0) |
800 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.2) | 16 (14.3) | 16 (13.6) |
1000 | 16 (16) | 16 (16) | 16 (16) | 16 (16) | 16 (15.8) | 16 (14.9) | 16 (14.2) | 16 (13.3) |
2000 | 16 (15.9) | 16 (14.9) | 16 (15.3) | 16 (15.2) | 16 (14.8) | 16 (14.5) | 16 (13.5) | 15.2 (12.6) |
4000 | 16 (13.0) | 16 (12.6) | 15.7 (12.9) | 16 (13.1) | 15.6 (13.0) | 15.5 (12.9) | 14.4 (11.9) | 13.6 (10.9) |
The ADS114S06B and ADS114S08B are precision 16-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs) with an integrated analog front-end (AFE) to simplify precision sensor connections. The ADC provides output data rates from 2.5 SPS to 4000 SPS for flexibility in resolution and data rates over a wide range of applications. The low-noise and low-drift architecture make these devices suitable for precise measurement of low-voltage sensors, such as load cells and temperature sensors.
The ADS114S0xB incorporates several features that simplify precision sensor measurements. Key integrated features include:
As described in the Functional Block Diagram section, these devices provide 12 (ADS114S08B) or six (ADS114S06B) analog inputs that are configurable as either single-ended inputs, differential inputs, or any combination of the two. Many of the analog inputs have additional features as programmed by the user. The analog inputs can be programmed to enable the following extended features:
Following the input multiplexer (MUX), the ADC features a high input-impedance, low-noise, programmable gain amplifier (PGA), eliminating the need for an external amplifier. The PGA gain is programmable from 1 to 128 in binary steps. The PGA can be bypassed to allow the input range to extend 50 mV below ground or above supply.
An inherently stable ΔΣ modulator measures the ratio of the input voltage to the reference voltage to provide the ADC result. The ADC operates with the internal 2.5-V reference, or with up to two external reference inputs. The external reference inputs can be continuously monitored for low voltage. The REFOUT pin provides the buffered 2.5-V internal voltage reference output that can be used to bias external circuitry.
The digital filter provides settled data with 50-Hz and 60-Hz line-cycle rejection at data rates of 2.5 SPS, 5 SPS, 10 SPS, and 20 SPS, 50-Hz rejection at data rates of 16.6 SPS and 50 SPS, and 60-Hz rejection at a data rate of 60 SPS.
Two programmable excitation current sources provide bias to resistive sensors [such as resistance temperature detectors (RTDs) or thermistors]. The ADC integrates several system monitors for read back, such as temperature sensor and supply monitors. Four GPIO pins are available as either dedicated pins (ADS114S06B) or combined with analog input pins (ADS114S08B).
The ADS114S0xB system clock is either provided by the internal low-drift, 4.096-MHz oscillator or an external clock source on the CLK input.
The SPI-compatible serial interface is used to read the conversion data and also to configure and control the ADC. The serial interface consists of four signals: CS, SCLK, DIN, and DOUT/DRDY. The dual function DOUT/DRDY output indicates when conversion data are ready and also provides the data output. The serial interface can be implemented with as little as three connections by tying CS low. Start ADC conversions with either the START/SYNC pin or with commands. The ADC can be programmed for a continuous conversion mode or to perform single-shot conversions.
The AVDD analog supply operates with bipolar supplies from ±1.5 V to ±2.625 V or with a unipolar supply from 2.7 V to 5.25 V. For unipolar-supply operation, use the VBIAS voltage to bias isolated (floating) sensors. The digital supplies operate with unipolar supplies only. The DVDD digital power supply operates from 2.7 V to 3.6 V and the IOVDD supply operates from DVDD to 5.25 V.
The ADS114S0xB contains a flexible input multiplexer; see Figure 42. Select any of the six (ADS114S06B) or 12 (ADS114S08B) analog inputs as the positive or negative input for the PGA using the MUX_P[3:0] and MUX_N[3:0] bits in the input multiplexer register (02h). In addition, AINCOM can be selected as the positive or negative PGA input. AINCOM is treated as a regular analog input, as is AINx. Use AINCOM in single-ended measurement applications as the common input for the other analog inputs.
The multiplexer also routes the excitation current sources to drive resistive sensors (bridges, RTDs, and thermistors) and can provide bias voltages for unbiased sensors (unbiased thermocouples for example) to analog input pins.
The ADS114S0xB also contains a set of system monitor functions measured through the multiplexer. The inputs can be shorted together at mid-supply [(AVDD + AVSS) / 2] to measure and calibrate the input offset of the analog front-end and the ADC. The system monitor also includes a temperature sensor that provides a measurement of the device temperature. The system monitor can also measure the analog and digital supplies, measuring [(AVDD – AVSS) / 4] for the analog supply or DVDD / 4 for the digital supply. Finally, the system monitor contains a set of burn-out current sources that pull the inputs to either supply if the sensor has burned out and has a high impedance so that the ADC measures a full-scale reading.
The multiplexer implements a break-before-make circuit. When changing the multiplexer channels using the MUX_P[3:0] and MUX_N[3:0] bits, the device first disconnects the PGA inputs from the analog inputs and connects them to mid-supply for 2 · tCLK. In the next step, the PGA inputs connect to the selected new analog input channels. This break-before-make behavior ensures the ADC always starts from a known state and that the analog inputs are not momentarily shorted together.
Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. The absolute voltage on any input must stay within the range provided by Equation 3 to prevent the ESD diodes from turning on:
External Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an unselected input on the device can affect conversions taking place on other input pins.
The ADS114S06B and ADS114S08B feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). Figure 43 shows a simplified diagram of the PGA. The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter and an antialiasing filter on the output.
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 using the GAIN[2:0] bits in the gain setting register (03h). Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4:
Table 3 shows the corresponding full-scale ranges when using the internal 2.5-V reference.
GAIN SETTING | FSR |
---|---|
1 | ±2.5 V |
2 | ±1.25 V |
4 | ±0.625 V |
8 | ±0.313 V |
16 | ±0.156 V |
32 | ±0.078 V |
64 | ±0.039 V |
128 | ±0.020 V |
The PGA must be enabled with the PGA_EN[1:0] bits of the gain setting register (03h). Setting these bits to 00 powers down and bypasses the PGA. A setting of 01 enables the PGA. The 10 and 11 settings are reserved and must not be written to the device.
With the PGA enabled, gains 64 and 128 are established in the digital domain. When the device is set to 64 or 128, the PGA is set to a gain of 32, and additional gain is established with digital scaling. The input-referred noise does still improve compared to the gain = 32 setting because the PGA is biased with a higher supply current to reduce noise.
As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded. The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA output. The specified minimum and maximum absolute input voltages (VAINP and VAINN) depend on the PGA gain, the maximum differential input voltage (VINMAX), and the tolerance of the analog power-supply voltages (AVDD and AVSS). Use the maximum voltage expected in the application for VINMAX. As shown in Equation 5, the absolute positive and negative input voltages must be within the specified range:
where
As mentioned in the previous section, PGA gain settings of 64 and 128 are scaled in the digital domain and are not implemented with the amplifier. When using the PGA in gains of 64 and 128, set the gain in Equation 5 to 32 to calculate the absolute input voltage range.
Figure 44 graphically shows the relationship between the PGA input to the PGA output. The PGA output voltages (VOUTP, VOUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the PGA output voltages must not exceed AVDD – 0.15 V or AVSS + 0.15 V. The diagram depicts a positive differential input voltage that results in a positive differential output voltage.
Download the ADS1x4S0x design calculator from www.ti.com. This calculator can be used to determine the input voltage range of the PGA.
At a gain of 1, the device can be configured to disable and bypass the low-noise PGA. Disabling the PGA lowers the overall power consumption and also removes the restrictions of Equation 5 for the input voltage range. If the PGA is bypassed, the ADC absolute input voltage range extends beyond the AVDD and AVSS power supplies, allowing input voltages at or below ground. Equation 6 shows the absolute input voltage range when the PGA is bypassed:
In order to measure single-ended signals that are referenced to AVSS (AINP = VIN, AINN = AVSS), the PGA must be bypassed. The PGA is bypassed and powered down by setting the PGA_EN[1:0] bits to 00 in the gain setting register (03h).
For signal sources with high output impedance, external buffering may still be necessary. Active buffers introduce noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.
The devices require a reference voltage for operation. The ADS114S0xB offers an integrated low-drift 2.5-V reference. For applications that require a different reference voltage value or a ratiometric measurement approach, the ADS114S08B offers two differential reference input pairs (REFP0, REFN0 and REFP1, REFN1). The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are dedicated reference inputs, whereas REFP1 and REFN1 are shared with inputs AIN6 and AIN7 (respectively) on the ADS114S08B. The specified external reference voltage range is 0.5 V to AVDD. The reference voltage is shown in Equation 7, where V(REFPx) and V(REFNx) are the absolute positive and absolute negative reference voltages.
The polarity of the reference voltage internal to the ADC must be positive. The magnitude of the reference voltage together with the PGA gain establishes the ADC full-scale differential input range as defined by
FSR = ±VREF / Gain.
Figure 45 shows the block diagram of the reference multiplexer. The ADC reference multiplexer selects between the internal reference and two external references (REF0 and REF1). The reference multiplexer is programmed with the REFSEL[1:0] bits in the reference control register (05h). By default, the external reference pair REFP0, REFN0 is selected.
The ADC integrates a precision, low-drift, 2.5-V reference. The internal reference is enabled by setting REFCON[1:0] to 10 (reference is always on) or 01 (reference is on, but powers down in power-down mode) in the reference control register (05h). By default, the internal voltage reference is powered down. To select the internal reference for use with the ADC, set the REFSEL[1:0] bits to 10. The REFOUT pin provides a buffered reference output voltage when the internal reference voltage is enabled. The negative reference output is the REFCOM pin; see Figure 45. Connect a capacitor in the range of 1 μF to 47 μF between REFOUT and REFCOM. Larger capacitor values help filter more noise at the expense of a longer reference start-up time.
The capacitor is not required if the internal reference is not used. However, the internal reference must be powered on if using the IDACs.
The internal reference requires a start-up time, as shown in Table 4, that must be accounted for before starting a conversion.
REFOUT CAPACITOR | SETTLING ERROR | SETTLING TIME (ms) |
---|---|---|
1 µF | 0.01% | 4.5 |
0.001% | 5.9 | |
10 µF | 0.01% | 4.9 |
0.001% | 6.3 | |
47 µF | 0.01% | 5.5 |
0.001% | 7.0 |
The ADS114S0xB provides two external reference inputs selectable through the reference multiplexer. The reference inputs are differential with independent positive and negative inputs. REFP0 and REFN0 or REFP1 and REFN1 can be selected as the ADC reference. REFP1 and REFN1 are shared inputs with analog pins AIN6 and AIN7 in the ADS114S08B.
Without buffering, the reference input impedance is approximately 250 kΩ. The reference input current can lead to possible errors from either high reference source impedance or through reference input filtering. To reduce the input current, use either internal or external reference buffers. In most applications external reference buffering is not necessary.
Connect a bypass capacitor across the external reference input pins if an external reference is used. Follow the specified absolute and differential reference voltage requirements.
The device has two individually selectable reference input buffers to lower the reference input current. Use the REFP_BUF and REFN_BUF bits in the reference control register (05h) to enable or disable the positive and negative reference buffers respectively. These bits are active low. Writing a 1 to REFP_BUF or REFN_BUF disables the reference buffers.
The reference buffers are recommended to be disabled when the internal reference is selected for measurements. The positive reference buffer is recommended to be disabled when REFPx is at AVDD and the negative reference buffer is recommended to be disabled when REFNx is at AVSS.
The ADS114S0xB system clock is either provided by the internal low-drift 4.096-MHz oscillator or an external clock source on the CLK input. Use the CLK bit within the data rate register (04h) to select the internal
4.096-MHz oscillator or an external clock source.
The device defaults to using the internal oscillator. If the device is reset (from either the RESET pin, or the RESET command), then the clock source returns to using the internal oscillator.
A delta-sigma (ΔΣ) modulator is used in the devices to convert the analog input voltage into a pulse code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 16, where fCLK is either provided by the internal 4.096-MHz oscillator or the external clock source.
The devices offer digital filter options for decimation of the digital data stream coming from the delta-sigma modulator. The implementation of the digital filter is determined by the data rate setting. Figure 46 shows the digital filter implementation.
The low-latency digital filter is a finite impulse response (FIR) filter that provides settled data, given that the analog input signal has settled to the final value before the conversion is started. This digital filter implementation is especially useful when multiple channels must be scanned in minimal time.
NOTE:
LL filter = low-latency filter.The device requires a set number of modulator clocks to output a single ADC conversion data. This number is known as the oversampling ratio (OSR). The OSR of the digital filter is set using the DR[3:0] bits in the data rate register. Equation 8 determines the data rate.
Table 5 shows the relationship between the data rate and oversampling ratio.
NOMINAL DATA RATE
(SPS)(1) |
DATA RATE REGISTER
DR[3:0] |
OVERSAMPLING
RATIO(2) |
---|---|---|
2.5 | 0000 | 102400 |
5 | 0001 | 51200 |
10 | 0010 | 25600 |
16.6 | 0011 | 15360 |
20 | 0100 | 12800 |
50 | 0101 | 5120 |
60 | 0110 | 4264 |
100 | 0111 | 2560 |
200 | 1000 | 1280 |
400 | 1001 | 640 |
800 | 1010 | 320 |
1000 | 1011 | 256 |
2000 | 1100 | 128 |
4000 | 1101 | 64 |
The digital filter provides many data rate options for rejecting 50-Hz and 60-Hz line cycle noise. At data rates of 2.5 SPS, 5 SPS, 10 SPS, and 20 SPS, the filter rejects both 50-Hz and 60-Hz line frequencies. At data rates of 16.6 SPS and 50 SPS, the filter has a notch at 50 Hz. At a 60-SPS data rate, the filter has a notch at 60 Hz.
For detailed frequency response plots showing line cycle noise rejection, download the ADS1x4S0x design calculator from www.ti.com.
Figure 47 to Figure 61 illustrate the frequency response of the digital filter for different data rates. Table 6 lists the bandwidth of the digital filter for each data rate.
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
fCLK = 4.096 MHz |
NOMINAL DATA RATE (SPS)(1) | –3-dB BANDWIDTH (Hz)(1) |
---|---|
2.5 | 1.1 |
5 | 2.2 |
10 | 4.7 |
16.6 | 7.4 |
20 | 13.2 |
50 | 22.1 |
60 | 26.6 |
100 | 44.4 |
200 | 89.9 |
400 | 190 |
800 | 574 |
1000 | 717 |
2000 | 1434 |
4000 | 2868 |
The digital filter notches and output data rate scale proportionally with the clock frequency. For example, a notch that appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. The internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate, conversion time, and filter notches consequently vary by the same percentage. Consider using an external precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.
The amount of time required to receive data from the ADC depends on more than just the nominal data rate of the device. The data period also depends on the mode of operation and other configurations of the device. In normal operation, the data settles in one data period. However, a small amount of latency exists to set up the device, calculate the conversion data from the modulator samples, and other overhead that adds time to the conversion. For this reason, the first conversion data takes longer than subsequent data conversions.
Table 7 shows the conversion times for the digital filter for each ADC data rate and various conversion modes.
NOMINAL
DATA RATE(1) (SPS) |
FIRST DATA
FOR CONTINUOUS CONVERSION MODE OR SINGLE-SHOT CONVERSION MODE(2) |
SECOND AND SUBSEQUENT
CONVERSIONS FOR CONTINUOUS CONVERSION MODE |
||
---|---|---|---|---|
ms | NUMBER OF
tMOD PERIODS |
ms | NUMBER OF
tMOD PERIODS |
|
2.5 | 406.559 | 104079 | 400 | 102400 |
5 | 206.559 | 52879 | 200 | 51200 |
10 | 106.559 | 27279 | 100 | 25600 |
16.6 | 60.309 | 15439 | 60 | 15360 |
20 | 56.559 | 14479 | 50 | 12800 |
50 | 20.211 | 5174 | 20 | 5120 |
60 | 16.965 | 4343 | 16.66 | 4264 |
100 | 10.211 | 2614 | 10 | 2560 |
200 | 5.211 | 1334 | 5 | 1280 |
400 | 2.711 | 694 | 2.5 | 640 |
800 | 1.461 | 374 | 1.25 | 320 |
1000 | 1.211 | 310 | 1 | 256 |
2000 | 0.711 | 182 | 0.5 | 128 |
4000 | 0.461 | 118 | 0.25 | 64 |
Each data period consists of time required for the modulator to sample the analog inputs. However, there is additional time required before the samples become an ADC conversion result.
When a new conversion is started, there is a configuration delay time of 14 · tMOD (where tMOD = 16 · tCLK) that is added before the conversion starts. This delay allows for additional settling time for external RC filters on the analog inputs and for the antialiasing filter after the PGA. The configuration delay occurs at the start of a new conversion after a START command is sent, the START/SYNC pin is taken high, or a WREG command is sent to change any configuration register from address 03h to 07h (as described in the WREG section).
Also, overhead time is needed to convert the modulator samples into an ADC conversion result. This overhead time includes any necessary offset or gain compensation after the digital filter accumulates a data result. The first conversion when the device is in continuous conversion mode (just as in single-shot conversion mode) includes the configuration delay, the modulator sampling time, and the overhead time. The second and subsequent conversions are the normal data period (period as given by the inverse of the data rate).
Figure 62 shows the time sequence for the ADC in both continuous conversion and single-shot conversion modes.
If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50-Hz and
60-Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and can lead to inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line-coupled noise for data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired level of line cycle rejection. Table 8 summarizes the ADC 50-Hz and 60-Hz line-cycle rejection based on ±1-Hz and ±2-Hz tolerance of power-line frequency. The best possible power-line rejection is provided by using an accurate ADC clock.
DATA RATE (SPS)(1) | DIGITAL FILTER LINE CYCLE REJECTION (dB) | |||
---|---|---|---|---|
50 Hz ± 1 Hz | 60 Hz ± 1 Hz | 50 Hz ± 2 Hz | 60 Hz ± 2 Hz | |
2.5 | –113.7 | –95.4 | –97.7 | –92.4 |
5 | –111.9 | –95.4 | –87.6 | –81.8 |
10 | –111.5 | –95.4 | –85.7 | –81.0 |
16.6 | –33.8 | –20.9 | –27.8 | –20.8 |
20 | –95.4 | –95.4 | –75.5 | –80.5 |
50 | –33.8 | –15.5 | –27.6 | –15.1 |
60 | –13.4 | –35.0 | –12.6 | –29.0 |
The ADS114S0xB incorporates two integrated, matched current sources (IDAC1, IDAC2). The current sources provide excitation current to resistive temperature devices (RTDs), thermistors, diodes, and other resistive sensors that require constant current biasing. The current sources are programmable to output values between 10 μA to 2000 μA using the IMAG[3:0] bits in the excitation current register 1 (06h). Each current source can be connected to any of the analog inputs AINx as well as the REFP1 and REFN1 inputs for the ADS114S06B. Both current sources can also be connected to the same pin. The routing of the IDACs is configured by the I1MUX[3:0] and I2MUX[3:0] bits in the excitation current register 2 (07h). In three-wire RTD applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see the Typical Application section for more details). Figure 63 details the IDAC connection through the input multiplexer.
The internal reference must be enabled for IDAC operation. As with any current source, the IDAC requires voltage headroom to the positive supply to operate. This voltage headroom is the compliance voltage. When driving resistive sensors and biasing resistors, take care not to exceed the compliance voltage of the IDACs, otherwise the specified accuracy of the IDAC current may not be met. For IDAC compliance voltage specifications, see the Electrical Characteristics table.
The ADS114S0xB provides an internal bias voltage generator, VBIAS, that is set to (AVDD + AVSS) / 2. The bias voltage is internally buffered and can be established on the analog inputs AIN0 to AIN5 and AINCOM using the VB_AINx bits in the sensor biasing register (08h). A typical use case for VBIAS is biasing unbiased thermocouples to within the common-mode voltage range of the PGA. Figure 64 shows a block diagram of the VBIAS voltage generator and connection diagram.
The start-up time of the VBIAS voltage depends on the pin load capacitance. The total capacitance includes any capacitance connected from VBIAS to AVDD, AVSS, and ground. Table 9 lists the VBIAS voltage settling times for various external load capacitances. Ensure the VBIAS voltage is fully settled before starting a conversion.
LOAD CAPACITANCE | SETTLING TIME |
---|---|
0.1 µF | 280 µs |
1 µF | 2.8 ms |
10 µF | 28 ms |
The ADS114S0xB provides a set of system monitor functions. These functions measure the device temperature, analog power supply, digital power supply, or use current sources to detect sensor malfunction. System monitor functions are enabled through the SYS_MON[2:0] bits of the system control register (09h).
On-chip diodes provide temperature-sensing capability. Enable the internal temperature sensor by setting SYS_MON[2:0] = 010 in the system control register (09h). The temperature sensor outputs a voltage proportional to the device temperature as specified in the Electrical Characteristics table.
When measuring the internal temperature sensor, the analog inputs are disconnected from the ADC and the output voltage of the temperature sensor is routed to the ADC for measurement using the selected PGA gain, data rate, and voltage reference. If enabled, PGA gain must be limited to 4 for the temperature sensor measurement to remain within the allowed absolute input voltage range of the PGA. As a result of the low device junction-to-PCB thermal resistance (RθJB), the internal device temperature closely tracks the printed circuit board (PCB) temperature.
The ADS114S0xB provides a means for monitoring both the analog and digital power supply (AVDD and DVDD). The power-supply voltages are divided by a resistor network to reduce the voltages to within the ADC input range. The reduced power-supply voltage is routed to the ADC input multiplexer. The analog (VANLMON) and digital (VDIGMON) power-supply readings are scaled by Equation 9 and Equation 10, respectively:
Enable the supply voltage monitors using the SYS_MON[2:0] bits in the system control register (09h). Setting SYS_MON[2:0] to 011 measures VANLMON, and setting SYS_MON[2:0] to 100 measures VDIGMON.
When the supply voltage monitor is enabled, the analog inputs are disconnected from the ADC and the PGA gain is set to 1, regardless of the GAIN[2:0] bit values in the gain setting register (03h). Supply voltage monitor measurements can be done with either the PGA enabled or PGA disabled via the PGA_EN[1:0] register. The reference voltage must be larger than the power-supply measurements shown in Equation 9 and Equation 10 to obtain valid power-supply monitor readings.