SBASAH6A March   2022  – October 2022 ADS117L11

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 6.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 6.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 6.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  Offset Error Measurement
    2. 7.2  Offset Drift Measurement
    3. 7.3  Gain Error Measurement
    4. 7.4  Gain Drift Measurement
    5. 7.5  NMRR Measurement
    6. 7.6  CMRR Measurement
    7. 7.7  PSRR Measurement
    8. 7.8  INL Error Measurement
    9. 7.9  THD Measurement
    10. 7.10 SFDR Measurement
    11. 7.11 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input (AINP, AINN)
        1. 8.3.1.1 Input Range
      2. 8.3.2 Reference Voltage (REFP, REFN)
        1. 8.3.2.1 Reference Voltage Range
      3. 8.3.3 Clock Operation
        1. 8.3.3.1 Internal Oscillator
        2. 8.3.3.2 External Clock
      4. 8.3.4 Modulator
      5. 8.3.5 Digital Filter
        1. 8.3.5.1 Wideband Filter
        2. 8.3.5.2 Low-Latency Filter (Sinc)
          1. 8.3.5.2.1 Sinc4 Filter
          2. 8.3.5.2.2 Sinc4 + Sinc1 Filter
          3. 8.3.5.2.3 Sinc3 Filter
          4. 8.3.5.2.4 Sinc3 + Sinc1 Filter
      6. 8.3.6 Power Supplies
        1. 8.3.6.1 AVDD1 and AVSS
        2. 8.3.6.2 AVDD2
        3. 8.3.6.3 IOVDD
        4. 8.3.6.4 Power-On Reset (POR)
        5. 8.3.6.5 CAPA and CAPD
      7. 8.3.7 VCM Output Voltage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Scalable Speed Modes
      2. 8.4.2 Idle Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Reset
        1. 8.4.5.1 RESET Pin
        2. 8.4.5.2 Reset by SPI Register Write
        3. 8.4.5.3 Reset by SPI Input Pattern
      6. 8.4.6 Synchronization
        1. 8.4.6.1 Synchronized Control Mode
        2. 8.4.6.2 Start/Stop Control Mode
        3. 8.4.6.3 One-Shot Control Mode
      7. 8.4.7 Conversion-Start Delay Time
      8. 8.4.8 Calibration
        1. 8.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 9h, Ah, Bh)
        2. 8.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        3. 8.4.8.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface (SPI)
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Serial Data Input (SDI)
        4. 8.5.1.4 Serial Data Output/Data Ready (SDO/DRDY)
      2. 8.5.2 SPI Frame
      3. 8.5.3 SPI CRC
      4. 8.5.4 Register Map CRC
      5. 8.5.5 Full-Duplex Operation
      6. 8.5.6 Device Commands
        1. 8.5.6.1 No-Operation
        2. 8.5.6.2 Read Register Command
        3. 8.5.6.3 Write Register Command
      7. 8.5.7 Read Conversion Data
        1. 8.5.7.1 Conversion Data
        2. 8.5.7.2 Data Ready
          1. 8.5.7.2.1 DRDY
          2. 8.5.7.2.2 SDO/DRDY
          3. 8.5.7.2.3 DRDY Bit
          4. 8.5.7.2.4 Clock Counting
        3. 8.5.7.3 STATUS Header
      8. 8.5.8 Daisy-Chain Operation
      9. 8.5.9 3-Wire SPI Mode
        1. 8.5.9.1 3-Wire SPI Mode Frame Reset
    6. 8.6 Registers
      1. 8.6.1  DEV_ID Register (Address = 0h) [reset = 01h]
      2. 8.6.2  REV_ID Register (Address = 1h) [reset = xxh]
      3. 8.6.3  STATUS Register (Address = 2h) [reset = x1100xxxb]
      4. 8.6.4  CONTROL Register (Address = 3h) [reset = 00h]
      5. 8.6.5  MUX Register (Address = 4h) [reset = 00h]
      6. 8.6.6  CONFIG1 Register (Address = 5h) [reset = 00h]
      7. 8.6.7  CONFIG2 Register (Address = 6h) [reset = 00h]
      8. 8.6.8  CONFIG3 Register (Address = 7h) [reset = 00h]
      9. 8.6.9  CONFIG4 Register (Address = 8h) [reset = 08h]
      10. 8.6.10 OFFSET2, OFFSET1, OFFSET0 Registers (Addresses = 9h, Ah, Bh) [reset = 00h, 00h, 00h]
      11. 8.6.11 GAIN2, GAIN1, GAIN0 Registers (Addresses = Ch, Dh, Eh) [reset = 40h, 00h, 00h]
      12. 8.6.12 CRC Register (Address = Fh) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
      4. 9.1.4 Simultaneous-Sampling Systems
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5.1 Wideband Filter

The wideband filter is a multistage FIR filter design featuring linear phase response, low pass-band ripple, narrow transition band, and high stop-band attenuation. Because of the excellent frequency domain performance, the wideband filter is effective for measuring ac signals. The ADC provides eight programmable oversampling ratios (OSR) and two speed modes, offering a range of data rates, resolution, and device power consumption to select from.

Figure 8-8 through Figure 8-12 illustrate the frequency response of the wideband filter. Figure 8-8 shows the pass-band ripple. Figure 8-9 shows the detailed frequency response at the transition band.

GUID-304A7D06-C916-4141-AADD-176616CBBBA6-low.gifFigure 8-8 Wideband Filter Pass-Band Ripple
GUID-888A5970-EF00-4428-8669-79C35AC8C970-low.gifFigure 8-9 Wideband Filter Transition Band

Figure 8-10 shows the frequency response to fDATA for OSR ≥ 64. The stop band begins at fDATA / 2 to prevent aliasing at the Nyquist frequency. Figure 8-11 shows the stop-band attenuation to fMOD for OSR = 32. In the stop-band region, out-of-band input frequencies intermodulate with multiples of the chop frequency at fMOD / 32, creating a pattern of response peaks that exceed the stop-band attenuation of the digital filter. The frequency width of each response peak is twice the bandwidth of the filter. Improved stop-band attenuation is provided by using an antialias filter at the ADC input. See the Section 9.2 section for details of a fourth-order antialias filter.

GUID-B9B903EA-24D0-4C9C-8466-E502C6AD47D6-low.gif
OSR ≥ 64
Figure 8-10 Wideband Filter Frequency Response
OSR = 32
Figure 8-11 Wideband Filter Stop-Band Attenuation

Figure 8-12 shows the filter response centered around fMOD. As shown, the filter response repeats at fMOD. If not removed by an antialiasing filter, input frequencies at fMOD appear as aliased frequencies in the pass band. Aliasing also occurs with input frequencies occurring at multiples of fMOD. The aliased frequency bands are defined by:

Equation 13. Aliased frequency bands: (N · fMOD) ± fBW

where:

  • N = 1, 2, 3, and so on
  • fMOD = Modulator sampling frequency
  • fBW = Filter bandwidth

Figure 8-12 Wideband Filter Frequency Response Centered at fMOD

The group delay of the filter is the time for a continuous input signal to propagate from the filter input to the filter output. Because the filter is a linear-phase design, the envelope of a complex input signal is undistorted by the filter. The group delay (expressed in units of time) is constant versus frequency equal to the value = 34 / fDATA. After a step change is applied to the ADC input (when synchronous to DRDY falling edge), fully settled data occurs 68 data periods later. Figure 8-13 illustrates the filter group delay (34 / fDATA) and the settling time of a step input (68 / fDATA).

Figure 8-13 Wideband Filter Step Response

The digital filter is restarted when the ADC is synchronized. The ADC suppresses the first 68 conversion periods until the filter is fully settled. There is no need to discard data after synchronization. The duration of data suppression is the conversion latency time as listed in the latency time column of Table 8-3. A 0.4-μs fixed overhead time is incurred for all data rates. If a step change input is applied without synchronizing the ADC, then the next 69 conversions are partially settled data.

Table 8-3 Wideband Filter
OSRDATA RATE (kSPS)–0.1-dB FREQUENCY (kHz)–3-dB FREQUENCY (kHz)LATENCY TIME (µs)(1)
HIGH-SPEED MODE (fCLK = 25.6 MHz)
32400165174.96170.6
6420082.587.48340.6
12810041.2543.74680.6
2565020.62521.871360.6
5122510.31210.9352720.6
102412.55.1565.4675440.6
20146.252.5782.73410880.6
40963.1251.2891.36721760.6
LOW-SPEED MODE (fCLK = 3.2 MHz)
325020.62521.871364.8
642510.31210.9352724.8
12812.55.1565.4675444.8
2566.252.5782.73410884.8
5123.1251.2891.36721764.8
10241.56250.6450.68343524.8
20480.781250.3220.34287044.8
40960.3906250.1610.171174084.8
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.