SBASAH6A March   2022  – October 2022 ADS117L11

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 6.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 6.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 6.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  Offset Error Measurement
    2. 7.2  Offset Drift Measurement
    3. 7.3  Gain Error Measurement
    4. 7.4  Gain Drift Measurement
    5. 7.5  NMRR Measurement
    6. 7.6  CMRR Measurement
    7. 7.7  PSRR Measurement
    8. 7.8  INL Error Measurement
    9. 7.9  THD Measurement
    10. 7.10 SFDR Measurement
    11. 7.11 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input (AINP, AINN)
        1. 8.3.1.1 Input Range
      2. 8.3.2 Reference Voltage (REFP, REFN)
        1. 8.3.2.1 Reference Voltage Range
      3. 8.3.3 Clock Operation
        1. 8.3.3.1 Internal Oscillator
        2. 8.3.3.2 External Clock
      4. 8.3.4 Modulator
      5. 8.3.5 Digital Filter
        1. 8.3.5.1 Wideband Filter
        2. 8.3.5.2 Low-Latency Filter (Sinc)
          1. 8.3.5.2.1 Sinc4 Filter
          2. 8.3.5.2.2 Sinc4 + Sinc1 Filter
          3. 8.3.5.2.3 Sinc3 Filter
          4. 8.3.5.2.4 Sinc3 + Sinc1 Filter
      6. 8.3.6 Power Supplies
        1. 8.3.6.1 AVDD1 and AVSS
        2. 8.3.6.2 AVDD2
        3. 8.3.6.3 IOVDD
        4. 8.3.6.4 Power-On Reset (POR)
        5. 8.3.6.5 CAPA and CAPD
      7. 8.3.7 VCM Output Voltage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Scalable Speed Modes
      2. 8.4.2 Idle Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Reset
        1. 8.4.5.1 RESET Pin
        2. 8.4.5.2 Reset by SPI Register Write
        3. 8.4.5.3 Reset by SPI Input Pattern
      6. 8.4.6 Synchronization
        1. 8.4.6.1 Synchronized Control Mode
        2. 8.4.6.2 Start/Stop Control Mode
        3. 8.4.6.3 One-Shot Control Mode
      7. 8.4.7 Conversion-Start Delay Time
      8. 8.4.8 Calibration
        1. 8.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 9h, Ah, Bh)
        2. 8.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        3. 8.4.8.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface (SPI)
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Serial Data Input (SDI)
        4. 8.5.1.4 Serial Data Output/Data Ready (SDO/DRDY)
      2. 8.5.2 SPI Frame
      3. 8.5.3 SPI CRC
      4. 8.5.4 Register Map CRC
      5. 8.5.5 Full-Duplex Operation
      6. 8.5.6 Device Commands
        1. 8.5.6.1 No-Operation
        2. 8.5.6.2 Read Register Command
        3. 8.5.6.3 Write Register Command
      7. 8.5.7 Read Conversion Data
        1. 8.5.7.1 Conversion Data
        2. 8.5.7.2 Data Ready
          1. 8.5.7.2.1 DRDY
          2. 8.5.7.2.2 SDO/DRDY
          3. 8.5.7.2.3 DRDY Bit
          4. 8.5.7.2.4 Clock Counting
        3. 8.5.7.3 STATUS Header
      8. 8.5.8 Daisy-Chain Operation
      9. 8.5.9 3-Wire SPI Mode
        1. 8.5.9.1 3-Wire SPI Mode Frame Reset
    6. 8.6 Registers
      1. 8.6.1  DEV_ID Register (Address = 0h) [reset = 01h]
      2. 8.6.2  REV_ID Register (Address = 1h) [reset = xxh]
      3. 8.6.3  STATUS Register (Address = 2h) [reset = x1100xxxb]
      4. 8.6.4  CONTROL Register (Address = 3h) [reset = 00h]
      5. 8.6.5  MUX Register (Address = 4h) [reset = 00h]
      6. 8.6.6  CONFIG1 Register (Address = 5h) [reset = 00h]
      7. 8.6.7  CONFIG2 Register (Address = 6h) [reset = 00h]
      8. 8.6.8  CONFIG3 Register (Address = 7h) [reset = 00h]
      9. 8.6.9  CONFIG4 Register (Address = 8h) [reset = 08h]
      10. 8.6.10 OFFSET2, OFFSET1, OFFSET0 Registers (Addresses = 9h, Ah, Bh) [reset = 00h, 00h, 00h]
      11. 8.6.11 GAIN2, GAIN1, GAIN0 Registers (Addresses = Ch, Dh, Eh) [reset = 40h, 00h, 00h]
      12. 8.6.12 CRC Register (Address = Fh) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
      4. 9.1.4 Simultaneous-Sampling Systems
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Analog Input (AINP, AINN)

The analog input of the ADC is differential, with the input defined as a difference voltage: VIN = VAINP – VAINN. For best performance, drive the input with a differential signal with the common-mode voltage centered to mid-supply (AVDD1 + AVSS) / 2.

The ADC can accept either unipolar or bipolar input signals by configuring AVDD1 and AVSS accordingly. Figure 8-1 shows an example of a differential signal with the supplies configured to unipolar operation. Symmetric input voltage headroom is available when the common-mode voltage is at mid-supply (AVDD1 / 2). Use AVDD1 = 5 V and AVSS = 0 V for unipolar operation (AVDD1 can be reduced to 3 V in low-speed mode). The VCM output provides a buffered common-mode voltage to level-shift the output voltage in the external driver stage. Figure 8-2 shows an example of a differential signal configured for bipolar operation. The common-mode voltage of the signal is normally at 0 V. Use AVDD1 and AVSS = ±2.5 V for bipolar operation (AVDD and AVSS can be reduced to ±1.5 V in low-speed mode).

GUID-2D331AE3-6C48-465C-A12F-8E849EF08640-low.gifFigure 8-1 Unipolar Differential Input Signal
GUID-A4628548-E874-41C4-B300-8FEDD801A055-low.gifFigure 8-2 Bipolar Differential Input Signal

In both bipolar and unipolar power-supply configurations, the ADC can accept single-ended input signals by tying the AINN input to AVSS or ground, or to mid-supply. However, because AINN is now a fixed voltage, the voltage range of the ADC is limited by the input swing range of AINP (±2.5 V or 0 V to 5 V for a 5-V supply).

The simplified circuit of Figure 8-3 represents the analog input structure.

Figure 8-3 Analog Input Circuit

Diodes protect the ADC inputs from electrostatic discharge (ESD) events that occur during the manufacturing process and during printed circuit board (PCB) assembly when manufactured in an ESD-controlled environment. If the inputs are driven below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes may conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to the specified value.

The input multiplexer offers the option of normal or reverse input signal polarities. The multiplexer also provides two internal test modes to help verify ADC performance. The offset test mode is used to verify noise and offset error by providing a short to the ADC inputs. The resulting noise and offset voltage data are evaluated by the user. CMRR performance is tested using the CMRR test mode by applying a CMRR test signal to the AINP input. The resulting CMRR test data are also evaluated by the user. Table 8-1 shows the switch configurations of the input multiplexer circuit of Figure 8-3.

Table 8-1 Input Multiplexer Configurations
MUX[1:0] BITSSWITCHESDESCRIPTION
00bS1, S4Normal polarity input
01bS2, S3Reverse polarity input
10bS5, S6Internal noise and offset error test
11bS1, S5CMRR test using a signal applied to AINP

The device has optional input precharge buffers to reduce the charge required by capacitor CIN during the input sampling phase. When the capacitor is near full charge, the precharge buffers are bypassed (S7 and S8 of Figure 8-3 in up positions). The external signal driver then provides the fine charge to the capacitor. At the completion of the sample phase, the sampling capacitor is discharged by the modulator to complete the cycle, at which time the sample process repeats. The buffers reduce the transient input current required to charge CIN, therefore reducing the settling time requirement of the signal. Incomplete settling of the input signal can lead to degraded ADC performance. The input buffers are enabled by the AINP_BUF and AINN_BUF bits of the CONFIG1 register. In many cases, if AINN is tied to ground or to a low-impedance fixed potential, the AINN buffer can be disabled to reduce power consumption.

With the input precharge buffers disabled, the charge required by the input sampling capacitor can be modeled as an average input current flowing into the ADC inputs. As shown in Equation 11 and Equation 12, the input current is comprised of differential and absolute components.

Equation 11. Input Current (Differential Input Voltage) = fMOD · CIN · 106 (μA/V)

where:

  • fMOD = fCLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode)
  • CIN = 7.4 pF (1x input range), 3.6 pF (2x input range)

Equation 12. Input Current (Absolute Input Voltage) = fMOD·CCM · 106 (μA/V)

where:

  • fMOD = fCLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode)
  • CCM = 0.35 pF (1x input range), 0.17 pF (2x input range)


For fMOD = 12.8 MHz, CIN = 7.4 pF, and CCM = 0.35 pF, the input current resulting from differential voltage is 95 μA/V and the input current resulting from the absolute voltage is 4.5 μA/V. For example, if AINP = 4.5 V and AINN = 0.5 V, then VIN = 4 V. The total AINP input current = (4 V · 95 μA/V) + (4.5 V · 4.5 μA/V) = 400 μA, and the total AINN current is (–4 V · 95 μA/V) + (0.5 V · 4.5 μA/V) = –378 μA.

The charge demand of the input sampling capacitor requires the signal to settle within a half cycle at the modulator frequency t = 1 / (2 · fMOD). To satisfy this requirement, the driver bandwidth is typically required to be much larger than the original signal frequency. The bandwidth of the driver can be determined to be sufficient when the THD and SNR data sheet performance are achieved. In the low-speed mode of operation, the modulator sampling is eight times slower, therefore more time is available for driver settling.